51edd19e85
add U bit to misa register
2016-07-22 14:22:59 -07:00
75347eed56
some fixes and cleanup to stateless bridge
2016-07-21 19:51:26 -07:00
9168f35971
clean up the requirements in StatelessBridge
...
* No need to check that release ID bits and acquire ID bits the same
* Check that inner and outer coherence policies match
2016-07-21 19:41:56 -07:00
a43ad522dc
add clock override to tile constructor ( #42 )
...
useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
2016-07-21 17:56:52 -07:00
12067a3b8d
make sure outer probe and finish lines are disconnected
2016-07-21 15:15:44 -07:00
c38dff0855
add some more warnings about the StatelessBridge
2016-07-21 15:07:10 -07:00
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
eb9e998c08
Add ManagerToClientStatelessBridge
2016-07-21 13:49:16 -07:00
0a1cd64786
fix number of builtin Acquire types
2016-07-21 13:45:20 -07:00
ffe17cbb2b
bump uncore for L2 bugfix
2016-07-21 12:35:38 -07:00
20df74d138
generate more L1 voluntary releases in TraceGen
2016-07-21 12:33:55 -07:00
86e31be820
fix lockup from back to back releases with data
2016-07-21 12:06:58 -07:00
24ef4e6dea
make sure to use AND not OR for combining finished signals
2016-07-21 12:05:11 -07:00
d77d0ddc5d
rename CacheTest.scala to CacheFillTest.scala
2016-07-20 20:37:45 -07:00
d56362f04c
add configuration checks for TraceGen
2016-07-20 10:37:10 -07:00
959630630a
give LCG an inc signal and add object constructors
2016-07-20 10:36:28 -07:00
b013925ab0
make sure ReleaseRegression starts only on io.start
2016-07-19 15:42:45 -07:00
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
fa8317fec1
debug: add clock crossing primitives
2016-07-19 14:52:43 -07:00
577c73667b
use getSimpleName to dump out test names
2016-07-19 14:42:58 -07:00
1dac2930eb
fix bug in WriteMaskedPutBlockRegression
2016-07-19 14:42:23 -07:00
19b44ec95b
Bug fixes in SimpleHellaCacheIF and L2 agents
...
* SimpleHellaCacheIF now properly handles both the non-blocking data
cache and blocking data cache.
* SimpleHellaCacheIF maintains ordering of replayed requests
* L2 VoluntaryReleaseTracker sends voluntary release grant properly
* Coherence protocols now downgrade for probeCopy
2016-07-19 09:35:13 -07:00
bc39d52655
changes to multi-transaction timer
2016-07-18 18:26:18 -07:00
e406d1bd73
Make probeCopy have same behavior as probeDowngrade
2016-07-18 18:22:49 -07:00
c069e66056
Modify the RoCC interface to include status in the command queue. ( #41 )
...
This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.
This addresses the first half of #40 .
2016-07-18 17:40:50 -07:00
9eeb1112d4
fix Bufferless irel_vs_iacq_conflict signal
2016-07-18 17:38:20 -07:00
e5cccc0526
don't update xact_vol_irel if not a voluntary irel
2016-07-18 17:05:23 -07:00
2723b2f515
fix issues in SimpleHellaCacheIF and document the changes
2016-07-18 17:02:47 -07:00
40a146f625
HellaCacheArbiter passes through if n == 1
2016-07-18 17:01:29 -07:00
39a1ecbf3c
switch groundtest to merged master
2016-07-18 09:34:27 -07:00
359252fdc1
fix a width bug
2016-07-18 09:33:17 -07:00
6fc4236782
add atomic and prefetch drivers
2016-07-18 09:33:17 -07:00
2ec736ed67
reorder some code in the Nasti unit tests
2016-07-18 09:33:17 -07:00
3ea299b062
make unit test debug output more meaningful
2016-07-18 09:33:17 -07:00
def740406c
fix a few Driver bugs
2016-07-18 09:33:17 -07:00
8278a73e83
group unit tests by their tested interface
2016-07-18 09:33:17 -07:00
9c0fffdd1c
start constructing composable tilelink unit test drivers
2016-07-18 09:33:17 -07:00
c92732dcaa
rename MemoryTestDriver to NastiDriver
2016-07-18 09:33:16 -07:00
c906e6edde
some renaming
2016-07-18 09:33:16 -07:00
1c2bf6e938
make list of unit tests a a parameter
2016-07-18 09:33:16 -07:00
69eebaf362
factor out unit tests into separate package
2016-07-18 09:33:16 -07:00
4af6313288
TraceGen: Lookup -> MuxLookup
...
A recent commit to tracegen.scala introduced a call to BitPat() which
seems to mess up the subsequent call to Lookup(). (This function
seems undocumented so I'm not sure what's going on.) As a fix, I've
removed the call to BitPat() and replaced Lookup() with MuxLookup().
2016-07-17 22:28:18 +01:00
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
59d700bf66
fix combinational loop in NASTI -> HASTI converter
2016-07-15 18:45:37 -07:00
cff8de9814
Use new Mul/Div parameters vs UseFastMulDiv ( #48 )
...
* Use new Mul/Div parameters vs UseFastMulDiv
* Rename MulDivUnroll to MulUnroll
2016-07-15 15:41:20 -07:00
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
897e6ccf8a
fix Hasti and Smi converters
2016-07-15 15:39:00 -07:00
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
84098db81f
add a TileLinkTestRAM
2016-07-15 11:03:26 -07:00
7cf44f9b25
clean up WideCounter implementation
2016-07-15 00:51:01 -07:00
