Andrew Waterman
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
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Huy Vo
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e909093f37
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Henry Cook
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b9a9664de5
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uncore and rocket changes for new xact types
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2012-10-01 10:47:36 -07:00 |
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Andrew Waterman
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0f20771664
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rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
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Andrew Waterman
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b94e6915ab
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refactor IPIs; use new tohost/fromhost protocol
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2012-08-03 19:00:34 -07:00 |
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Andrew Waterman
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130fa95ed6
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expand HTIF's PCR register space
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2012-07-27 14:52:39 -07:00 |
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Andrew Waterman
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a5bea4364f
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memory system bug fixes
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2012-07-26 00:05:21 -07:00 |
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Andrew Waterman
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a21c355114
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fix htif split request/response
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2012-07-23 17:15:16 -07:00 |
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Yunsup Lee
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379f021359
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change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
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2012-07-22 18:26:02 -07:00 |
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Andrew Waterman
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f42c6afed2
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
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Andrew Waterman
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4e44ed7400
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allow back pressure on IPI requests
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2012-07-17 22:55:40 -07:00 |
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Andrew Waterman
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39d198ecdc
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fix htif handling of large memory reads
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2012-06-26 19:12:11 -07:00 |
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Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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c975c21e44
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views removed
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2012-06-06 12:51:26 -07:00 |
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Andrew Waterman
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
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Andrew Waterman
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b851f1b34c
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support maximum-MTU HTIF packets
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2012-05-03 21:11:43 -07:00 |
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Henry Cook
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3cdd166153
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Refactored coherence as member rather than trait. MI and MEI protocols.
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2012-04-10 00:09:58 -07:00 |
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Henry Cook
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0b4937f70f
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changed coherence message type names
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2012-04-09 23:29:31 -07:00 |
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Andrew Waterman
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7fa93da4f5
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add backup memory port (disabled for now)
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2012-03-25 15:49:32 -07:00 |
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Andrew Waterman
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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3a487ac89b
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improve htif<->pcr interface
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
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Andrew Waterman
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ab6c9350db
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fix minor coherence bugs
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2012-03-13 19:10:54 -07:00 |
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Andrew Waterman
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1492457df5
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add probe replies to HTIF
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2012-03-13 16:56:47 -07:00 |
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Henry Cook
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22726ae646
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icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
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2012-03-08 18:47:32 -08:00 |
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Andrew Waterman
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6e16b04ada
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implement transaction finish messages
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2012-03-06 15:48:08 -08:00 |
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Andrew Waterman
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5f12990dfb
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support memory transaction aborts
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2012-03-06 00:35:02 -08:00 |
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Henry Cook
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1b3307df32
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Removed has_data fields from all coherence messages, increased message type names to compensate
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2012-03-02 23:51:53 -08:00 |
|
Yunsup Lee
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8678b3d70c
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clean up ioDecoupled/ioPipe interface
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2012-03-01 20:48:46 -08:00 |
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Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Andrew Waterman
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c99f6bbeb7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
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Andrew Waterman
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2b1c07c723
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
|
Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
|
Andrew Waterman
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012028efaa
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fix fpga build
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2012-02-23 22:19:38 -08:00 |
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Andrew Waterman
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7034c9be65
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new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
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