695c4c5096
Support both Get and GetBlock on ROMSlave
2016-04-30 17:34:12 -07:00
491184a8f8
ERET -> xRET; remove mcfgaddr
2016-04-30 17:32:51 -07:00
5af98145b9
don't signal bad physical address on TLB miss
2016-04-30 17:31:46 -07:00
6f052a740c
Add TileLink BRAM slave
2016-04-29 14:10:44 -07:00
d0aa4c722d
More WIP on new memory map
2016-04-28 16:15:31 -07:00
cae4265f3b
Change mcfgaddr pointer
2016-04-28 16:14:05 -07:00
e4ace55d77
Address Map refactoring
2016-04-28 16:12:35 -07:00
1df68a25fd
Address Map refactoring
2016-04-28 16:08:58 -07:00
ed5bdf3c23
print the base address of each SCR as indicated
2016-04-28 16:31:56 +01:00
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
739cf07637
Remove mtime/mtimecmp
...
The RTC is now a device that lives on the MMIO bus.
2016-04-27 14:54:51 -07:00
81ff127dc3
Clean up TileLinkRecursiveInterconnect a bit
2016-04-27 14:53:11 -07:00
c8b1f0801b
Remove start address option from AddrMapEntries
...
It appears to never be used, and clutters things. The new invariant is
that AddrMaps are relative and AddrHashMaps are absolute.
2016-04-27 14:52:05 -07:00
d3dee2c6c6
support countSlaves on empty address maps
2016-04-27 14:51:52 -07:00
87cecc336f
Add new RTC as TileLink slave, not AXI master
2016-04-27 11:55:35 -07:00
fb5c38c186
Handle invalidate_lr in cache arbiter, not tile
2016-04-27 11:22:04 -07:00
b99db83e67
Avoid needless Vec generation
2016-04-27 00:28:39 -07:00
8acec8eb36
Remove dead code from BTB
2016-04-27 00:28:12 -07:00
eb0b5ec61e
Remove stats CSR
2016-04-27 00:16:21 -07:00
9044a4a4b7
Replace NastiROM with ROMSlave, which uses TileLink
...
I'm not wedded to the name.
2016-04-27 00:15:30 -07:00
356efe2fd5
Simplify TileLink Narrower
...
It's not necessary to use addr_beat to determine where to put the Grant
data. Just stripe it across all lanes.
This also gets rid of a dependence on addr_beat in Grant. If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
2016-04-26 16:44:54 -07:00
fe8c91f620
Fix IOMSHR state machine bug
...
Sending the finish too early causes the CPU response to get dropped.
attn @zhemao
2016-04-26 15:32:25 -07:00
5fd5b58743
Remove stats CSR
2016-04-26 15:31:32 -07:00
d93677a343
Support larger cache sets when not using VM
2016-04-26 15:31:32 -07:00
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
48170fd9aa
add default cases to configs that use CDEMatchError
...
this avoids filling in the stack trace every time
a config doesn't contain the parameter
2016-04-22 12:14:58 -07:00
f6e44b1348
avoid logical to physical header conversion overflow
2016-04-22 17:47:34 +01:00
f7af908969
put memory into the address map and no longer use MMIOBase
2016-04-21 18:53:16 -07:00
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
5e793427eb
use address map instead of MMIOBase
2016-04-21 15:38:43 -07:00
f9de99ed40
changes to match junctions no-mmio-base
2016-04-21 15:35:37 -07:00
6260ad56e8
stop using MMIOBase and encode cacheability in address map
2016-04-21 15:33:53 -07:00
325d3671c4
add write data id field for AXI3 compat
2016-04-20 09:21:43 -07:00
0cf6b1f118
merge ATOS changes from hurricane
2016-04-20 09:21:43 -07:00
c19931ba03
add technical report to readme
2016-04-19 16:17:50 -07:00
4afc9c69a0
streamline sbt
2016-04-19 14:22:22 -07:00
9b3faff5a5
add id field to write data channel in TL -> AXI converter
2016-04-19 09:46:31 -07:00
1967186a96
add id field to NastiWriteDataChannel
2016-04-19 09:39:45 -07:00
42c4d1e51f
add NastiMemoryDemux
2016-04-19 09:39:15 -07:00
0bf8d07aba
make AtosSerializedIO clock divisible
2016-04-19 09:39:15 -07:00
1dc8af894e
fix serializer/deserializer and add Atos serdes/desser
2016-04-19 09:39:15 -07:00
82cacfbc5e
add NastiMemoryDemux to unit tests
2016-04-19 09:34:42 -07:00
075fdfb847
use Atos serdes/desser in Atos unit test
2016-04-19 09:34:12 -07:00
ee66da603a
move AtosConverterTest into UnitTestSuite
2016-04-19 09:34:12 -07:00
d19aaf8d89
test AtoS conversions and SERDES
2016-04-19 09:33:05 -07:00
7c33d88861
Merge pull request #90 from ucb-bar/elaborate-once
...
Bump Chisel3, to elaborate circuits once
2016-04-18 21:04:55 -07:00
85c86994a0
Bump Chisel3, to elaborate circuits once
2016-04-18 14:54:17 -07:00
cbfd7fd13a
Remove tracegen scripts, now in groundtest
...
And bump groundtest.
2016-04-14 14:01:48 -07:00
c5838dd9b3
Fix narrow read/write behavior for AXI converters and fix L2 bugs
...
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.
There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.
There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
