Huy Vo
fdffb124e3
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476
fix to rocket vec_dpath, updating makefiles to run xcpt test cases
2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262
Further refinement of tag_match/tag_hit signals
2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1
fix way selection on D$ write upgrades
2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0
support non-power-of-2 queue sizes
...
need to manually wrap queue pointers.
2012-03-13 01:58:28 -07:00
Henry Cook
cbf7b13341
fix hit logic for amos
2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4
fixed cache controller flush unit deadlock
2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b
fixed abort bug
2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865
changes to the vector exception interface
2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d
add vector hold waits
2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e
don't stall on vector fences, keep replaying
2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80
bugfix in locking arbiter
2012-03-11 15:47:27 -07:00
Henry Cook
4ebf637642
More broadcast hub bugfixes
2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187
fix icache prefetch global_xact_id bug
2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d
going back to null coherence hub
2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526
fix D$ store-upgrade bug
...
loads to the same address as stores that cause an upgrade
could return the old value
2012-03-10 15:50:10 -08:00
Andrew Waterman
4f4b990a4f
fix null hub store ack bug
2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f
vector exception handler now handles prefetches correctly
2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e
fix signedness of zero fmul results
...
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0. Now we
add -0.0 if rs1*rs2 is negative.
2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0
fix D$ critical paths and fix verilog build
2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91
Fixed global_xact_id propagation bug
2012-03-09 11:05:44 -08:00
Henry Cook
9319130483
Special cased NTILES == 1 due to log2up revision
2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc
fix bug in fence.i and improve test
2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8
refactor D$ writebacks and flushes
...
MSHRs now arbitrate for writebacks and handle flushes.
2012-03-09 02:55:46 -08:00
Andrew Waterman
ff2e47f380
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd
major refactoring on vector exception interface
2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646
icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
2012-03-08 18:47:32 -08:00
Henry Cook
4d2e7172f6
Added require_ack field to TransactionReply bundle
2012-03-08 18:07:44 -08:00
Henry Cook
35c4bd4084
Hub addr comparison bug fix
2012-03-08 16:39:05 -08:00
Henry Cook
788ad327da
Fixed dependency queue bug in Broadcast Hub
2012-03-08 11:36:10 -08:00
Henry Cook
7f43dee0c9
PriorityEncoder apply() no longer has recursive depth param
2012-03-08 01:04:26 -08:00
Andrew Waterman
5a7c5772a8
clearly distinguish PPN and cache tag
2012-03-07 23:11:17 -08:00
Andrew Waterman
941873bad1
coherence hub fixes
2012-03-07 21:03:44 -08:00
Henry Cook
7deff5fbe2
Broadcast hub bug fixes for load uncached mem req and store uncached xact rep
2012-03-07 11:40:49 -08:00
Andrew Waterman
c09eeb7fd2
fix D$ next-state logic
...
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
2012-03-07 01:42:08 -08:00
Andrew Waterman
a0c9452b86
change D$ to use FourStateCoherence protocol
...
instead of ThreeStateIncoherence.
2012-03-07 01:26:35 -08:00
Andrew Waterman
6e2610b0ad
fix Mux1H for bundles
2012-03-06 23:38:36 -08:00
Yunsup Lee
81dcb194d3
new vector exception interface
2012-03-06 22:39:15 -08:00
Henry Cook
47a2097507
unified coherence trait functions
2012-03-06 17:33:11 -08:00
Henry Cook
3dd404dcf4
hub code cleanup
2012-03-06 17:01:47 -08:00
Henry Cook
c0ed010bc9
newTransactionOnMiss()
2012-03-06 15:54:41 -08:00
Henry Cook
962e5a54af
Added store dependency queues to BroadcastHub. Minor improvements to utils.
2012-03-06 15:54:41 -08:00
Andrew Waterman
499c5b4a2e
automatically infer MEM_TAG_BITS
2012-03-06 15:49:28 -08:00
Andrew Waterman
6e16b04ada
implement transaction finish messages
2012-03-06 15:48:08 -08:00
Yunsup Lee
dba99e07a9
set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4
2012-03-06 08:54:21 -08:00
Andrew Waterman
5f33ab24b0
fix merge conflict
...
oops :(
2012-03-06 02:02:53 -08:00
Andrew Waterman
5f12990dfb
support memory transaction aborts
2012-03-06 00:35:02 -08:00
Henry Cook
950b5cd900
Added aborted data dequeueing state machine for BroadcastHub
2012-03-05 17:44:30 -08:00
Henry Cook
5c66a6699c
Broadcast hub control logic bugfixes and code cleanup
2012-03-05 17:27:55 -08:00
Yunsup Lee
a950d526d2
add prefetch count queue
2012-03-05 12:09:41 -08:00
Yunsup Lee
d4ec7ff4d9
refined vector exception interface
2012-03-03 16:11:54 -08:00
Yunsup Lee
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
Yunsup Lee
f9fb3978ca
fix store prefetch bug, it no longer occupies an entry in the sdq
2012-03-03 15:14:59 -08:00
Henry Cook
1b3307df32
Removed has_data fields from all coherence messages, increased message type names to compensate
2012-03-02 23:51:53 -08:00
Henry Cook
35f97bf858
Filled out 4 state coherence functions for cache
2012-03-02 21:58:50 -08:00
Henry Cook
00989c58bd
Correction to probe reply w/ data handling
2012-03-02 17:20:22 -08:00
Andrew Waterman
1e1926ce63
flip direction of ioPipe to match ioDecoupled
2012-03-02 16:18:32 -08:00
Henry Cook
7406908d4a
BroadcastHub can be elaborated by C and vlsi backends
2012-03-02 12:19:27 -08:00
Yunsup Lee
54baa0713c
hack fence.g.cv to support waiting the control processor
2012-03-02 02:10:26 -08:00
Yunsup Lee
1054cec087
add vec countq interface
2012-03-02 00:43:32 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Andrew Waterman
6d03d75835
improve D$ internal interfaces
2012-03-01 20:20:15 -08:00
Andrew Waterman
28cacd953f
D$ cleanup - merge ReplayUnit and MSHRFile
2012-03-01 19:30:56 -08:00
Andrew Waterman
52101373e0
clean up D$ store data unit
2012-03-01 19:20:00 -08:00
Henry Cook
da39810bb2
Fixed elaboration errors in LockingArbiter and BoradcastHub. Fixed ioDecoupled direction error in XactTracker
2012-03-01 18:24:22 -08:00
Henry Cook
9d7707a0a2
Made xact_rep an ioValid, removed has_data member
2012-03-01 18:24:21 -08:00
Yunsup Lee
c7b01230f4
fix mul/div when waddr=0, can't believe torture didn't find this one
2012-03-01 10:15:27 -08:00
Henry Cook
c6162ac743
Unified hub ios. Fixed some hub elaboration errors.
2012-03-01 01:20:57 -08:00
Yunsup Lee
a8ef5e9e27
change NMSHR when HAVE_VEC is true
2012-03-01 01:07:47 -08:00
Yunsup Lee
6847160343
refactor arbiter priorities
2012-03-01 00:22:34 -08:00
Yunsup Lee
f641b44fb8
changes after the module uniquify bug fix
2012-02-29 22:00:59 -08:00
Henry Cook
813ffcbf3e
Finished broadcast hub with split mem req types. Untested.
2012-02-29 17:58:15 -08:00
Yunsup Lee
4939b72ba5
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
Yunsup Lee
20d0088f66
temporary fix to match bit widths for Mem
2012-02-29 17:09:31 -08:00
Henry Cook
008ad1f45b
Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low
2012-02-29 17:05:06 -08:00
Henry Cook
c723ef4c50
ioDecoupled now allows inner bundle to be used in covariant positions, i.e. it accepts subtypes
2012-02-29 16:46:16 -08:00
Andrew Waterman
c38065d0e8
clean up priority encoders
2012-02-29 16:13:14 -08:00
Andrew Waterman
b9ec69f8f5
add new Queue singleton
2012-02-29 14:21:42 -08:00
Andrew Waterman
012da6002e
replace tile memory interface with ioTileLink
...
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
2012-02-29 03:10:47 -08:00
Henry Cook
082b38d315
Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs.
2012-02-29 02:59:27 -08:00
Henry Cook
8ff6e21e3a
Fixed race between read resps/reps and write req/reps in null hub
2012-02-29 00:44:03 -08:00
Andrew Waterman
c99f6bbeb7
separate memory request command and data
...
also, merge some VLSI/C++ test harness functionality
2012-02-28 19:06:23 -08:00
Henry Cook
040aa9fe02
Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
2012-02-28 17:33:32 -08:00
Daiwei Li
3f998b1353
send vcfg and setvl to vu prefetch queues
2012-02-28 14:54:48 -08:00
Henry Cook
5cc10337b4
Null coherence hub. Begin work on internal tracker logic
2012-02-27 19:10:15 -08:00
Andrew Waterman
2b1c07c723
replace ioDCache with ioMem
2012-02-27 18:36:09 -08:00
Andrew Waterman
1d41a41afa
remove extraneous constants
2012-02-27 17:49:48 -08:00
Yunsup Lee
3d96a2d4f0
add fpu.dec.wen := false when HAVE_FPU is turned off
2012-02-27 14:00:58 -08:00
Henry Cook
f0588a0052
Added probe_req ready sigs, GenArray to Vec
2012-02-27 11:26:18 -08:00
Henry Cook
7a8f53a117
probe req transactors in coherence hub
2012-02-27 09:24:33 -08:00
Henry Cook
2275239f33
xact init transactors in coherence hub
2012-02-27 09:24:32 -08:00
Yunsup Lee
bfd0ae125e
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74
fix yet another AMO-related replay bug
2012-02-26 20:20:45 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98
simplify cpu-cache interface
2012-02-26 18:26:29 -08:00
Andrew Waterman
ad713a5d83
fix icache ram depth; new chisel
2012-02-26 17:51:46 -08:00
Yunsup Lee
f3bb02b2ea
refactored dmem arbiter
2012-02-26 17:38:08 -08:00
Huy Vo
93f41d3359
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-26 17:24:23 -08:00
Huy Vo
5b0f7ccf68
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
2012-02-26 17:24:08 -08:00
Yunsup Lee
766a039ffe
small changes to the dtlb arbiter
2012-02-26 16:19:50 -08:00
Daiwei Li
69260756bd
change ppn and vpn in dtlb from ufix to bits
2012-02-26 02:54:31 -08:00
Yunsup Lee
49efe4b744
now vu steals cycles from the fpu's fma alu
2012-02-26 01:55:07 -08:00
Daiwei Li
47dbc2a417
head should be working again
2012-02-26 00:30:50 -08:00
Daiwei Li
569698b824
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-25 22:05:30 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e
add vector exception infrastructure
2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318
massive refactoring of vector constants
2012-02-25 15:55:36 -08:00
Henry Cook
3980120279
More stylish bundle param names, some hub progress
2012-02-25 15:27:53 -08:00
Henry Cook
db6d480778
Better foldR
2012-02-25 15:27:09 -08:00
Henry Cook
df97de0fd3
Better abstraction of data bundles
2012-02-25 12:57:01 -08:00
Henry Cook
4fa31b300b
Added popcount util
2012-02-25 12:57:01 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007
refactor cpfences
2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34
fix (?) external memory request nack interface
2012-02-24 01:42:33 -08:00
Daiwei Li
477f3cde02
added prefetch queues for vu
2012-02-24 00:44:13 -08:00
Yunsup Lee
63939efd0c
fix ctrl vec iface hookup - final
2012-02-23 23:03:44 -08:00
Yunsup Lee
bf1e643913
fix ctrl vec iface hookup
2012-02-23 22:55:25 -08:00
Andrew Waterman
7b3cce79e3
allocate a primary miss on a prefetch
2012-02-23 22:40:24 -08:00
Yunsup Lee
2ea309cf80
bug fixes to ctrl_vec
2012-02-23 22:35:05 -08:00
Yunsup Lee
91a0bb6f61
add vector prefetch queues
2012-02-23 22:30:38 -08:00
Andrew Waterman
012028efaa
fix fpga build
2012-02-23 22:19:38 -08:00
Henry Cook
52da831aa3
finished xact_finish and xact_abort transactors in coherence hub
2012-02-23 18:12:50 -08:00
Henry Cook
1c1ce7d60b
finished xact_rep transactor in coherence hub
2012-02-23 17:50:02 -08:00
Andrew Waterman
5332bab6f1
expose FMA ports outside of FPU (for the VU)
2012-02-23 17:39:34 -08:00
Andrew Waterman
6ceaa0e80a
correct and simplify replay_next logic
2012-02-23 16:52:52 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Yunsup Lee
e53792a1eb
fix bug in rocket's vector datapath related to wakeup
2012-02-23 10:14:14 -08:00
Andrew Waterman
7c929afe2b
HTIF now controls CPU reset
2012-02-22 19:30:03 -08:00
Andrew Waterman
3eebf40310
nack CPU requests during any replay
2012-02-22 18:37:13 -08:00
Henry Cook
62837537f4
Improved TileIO organization, beginnings of hub implementation
2012-02-22 18:24:52 -08:00
Henry Cook
24a32c2811
Refining tilelink interface
2012-02-22 12:15:47 -08:00
Henry Cook
18bd0c232b
Added coherence message type enums
2012-02-22 12:15:47 -08:00
Daiwei Li
22f8dd0994
Hook up resp_type to vector unit
2012-02-21 18:20:32 -08:00
Andrew Waterman
cfd79c731b
add resp_type to ext_mem interface
2012-02-21 17:42:00 -08:00
Andrew Waterman
9a80adef50
only instantiate VI$ if HAVE_VEC
2012-02-21 15:53:19 -08:00
Andrew Waterman
c8f768c8b3
fix AMO replay bug
...
like the recent AMO bug fix, but affects stores too. oops.
2012-02-21 14:39:54 -08:00
Andrew Waterman
d5608b2728
fix AMO replay bug
...
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
2012-02-21 01:02:16 -08:00
Andrew Waterman
6135615104
unify cache backend interfaces; generify arbiter
2012-02-20 00:51:48 -08:00
Andrew Waterman
7034c9be65
new htif protocol and implementation
...
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Andrew Waterman
9af86633d7
invalidate I$ prefetcher when invalidating I$
2012-02-17 17:56:01 -08:00
Henry Cook
e555fd3fc4
Abstract class for coherence policies
2012-02-16 12:59:38 -08:00
Henry Cook
d46e59a16d
Abstract base nbcache class
2012-02-16 12:34:51 -08:00
Henry Cook
124efe5281
Replace nbcache manipulation of meta state bits with abstracted functions
2012-02-16 10:43:40 -08:00
Henry Cook
619929eba1
Added coherence tile function defs, with traits and constants
2012-02-16 00:16:45 -08:00
Andrew Waterman
1b5e39e7fc
fix bug in BTB
...
a BTB update followed by a taken branch could cause incorrect control flow.
2012-02-15 21:36:08 -08:00
Andrew Waterman
fc5ba769da
disable vector unit by default
2012-02-15 18:58:41 -08:00
Andrew Waterman
8b3b3abd3d
fix external memory request nack logic
2012-02-15 18:57:40 -08:00
Andrew Waterman
fe2c1d1321
add vec->ctrl fences
2012-02-15 18:31:19 -08:00
Yunsup Lee
82cd3625c2
add in vackq interface
2012-02-15 17:53:24 -08:00
Andrew Waterman
c13524ad3a
fix vcmdq full replay logic
2012-02-15 17:49:12 -08:00
Yunsup Lee
258d050e1b
add stall logic for vector command queues
2012-02-15 14:48:41 -08:00
Yunsup Lee
32bdf5098a
refactor vector control logic & datapath in the rocket core
2012-02-15 13:30:22 -08:00
Yunsup Lee
7c11c1406c
vector-vector add working!
2012-02-15 02:28:07 -08:00
Yunsup Lee
6bdf9dc513
hwacha integration: now it compiles correctly!
2012-02-14 23:34:57 -08:00
Yunsup Lee
a51c7cc927
new build system with updated chisel, hwacha
2012-02-14 19:43:59 -08:00
Andrew Waterman
0ec7767c13
declaring success on FPU for now
2012-02-14 19:11:57 -08:00
Andrew Waterman
297223a13c
squash subsequent external mem request after nack
2012-02-14 15:12:16 -08:00
Andrew Waterman
38c67e5a9e
add fmin.[s|d] and fmax.[s|d]
2012-02-14 06:37:18 -08:00
Andrew Waterman
ee9fc10668
add fcvt.s.d, fcvt.d.s
2012-02-14 06:03:43 -08:00
Andrew Waterman
ce202c73d1
add fsgnj[n|x].[s|d]
2012-02-14 04:24:35 -08:00
Andrew Waterman
1d604bcd49
remove top-level Makefile
...
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
2012-02-14 02:53:43 -08:00
Andrew Waterman
15dc2d8c40
add fp writeback arbitration logic
2012-02-14 00:32:25 -08:00
Henry Cook
0671a99712
NBcache works with associativities other than powers of 2
2012-02-13 21:44:32 -08:00
Henry Cook
6d36168183
Fixed two associative nbcache bugs, one in amo replays and one in the flush unit
2012-02-13 21:44:32 -08:00
Andrew Waterman
0366465cb1
parameterize the scoreboards
2012-02-13 18:12:23 -08:00
Andrew Waterman
6c2d8a37ae
remove a partial update that makes chisel barf
...
chisel regards it as a combinational loop, even though it isn't.
2012-02-13 16:45:29 -08:00
Andrew Waterman
c78c738f60
minor cleanups
2012-02-13 03:13:49 -08:00
Andrew Waterman
b5a19a54a3
add fcvt.[s|d].[w|l][u]
2012-02-13 02:01:26 -08:00
Andrew Waterman
a4a9d2312c
add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d]
2012-02-13 01:30:01 -08:00
Andrew Waterman
069037ff3a
add FP recoding
2012-02-12 23:31:50 -08:00
Andrew Waterman
25ecfb9bbc
clean up caches
...
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
2012-02-12 20:32:06 -08:00
Andrew Waterman
08b6517a23
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-12 20:12:53 -08:00
Andrew Waterman
9bb1558a34
WIP on FPU
2012-02-12 04:36:01 -08:00
Andrew Waterman
50a283d311
move store data generation into EX stage
...
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee
update to new chisel
2012-02-11 17:20:33 -08:00
Andrew Waterman
f8b937d590
fix 32-bit divider bug
...
thanks, torture!
also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
Andrew Waterman
03ee49f424
fix 32-bit AMOs to upper halves of 64-bit words
...
thanks, torture!
2012-02-09 03:31:47 -08:00
Yunsup Lee
f47d888feb
vvcfgivl and vsetvl works
2012-02-09 02:35:21 -08:00
Andrew Waterman
92493ad153
fix mul/div kill bug
...
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
Andrew Waterman
128ec567ed
make BTB fully associative; don't use it for JALR
...
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d
hook up the vector command queue
2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367
add external memory request interface for vec unit
2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25
initial vu integration
2012-02-08 21:43:45 -08:00
Andrew Waterman
10b5a0006c
fix mul/div to rd=0
2012-02-08 20:11:57 -08:00
Andrew Waterman
a1855b12c2
clean up queues
2012-02-08 17:55:05 -08:00
Andrew Waterman
990e3a1b34
fix fpu port direction bug
2012-02-08 15:19:26 -08:00
Andrew Waterman
b3f6f9a5fd
fix BTB misprediction check for negative addresses
...
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
Andrew Waterman
e9da2cf66a
improve id/ex datapath
...
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da
arbitrate for LLFU writebacks in MEM stage
2012-02-08 04:21:05 -08:00
Andrew Waterman
ebed56500e
fix mul/wb hazard checks
...
I erroneously assumed that those instructions set id_wen.
2012-02-08 01:56:11 -08:00
Andrew Waterman
5403d069e9
add fp loads/stores
2012-02-07 23:54:25 -08:00
Christopher Celio
1be9d15944
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
2012-02-07 14:07:42 -08:00
Andrew Waterman
fde8e3b696
clean up bypassing/hazard checking a bit
2012-02-06 17:26:45 -08:00
Henry Cook
41c4e10c37
Workaround for another frakking extraction error in the C backend. C and VLSI backends now both boot kernel with associativity on
2012-02-02 21:53:57 -08:00
Andrew Waterman
99a959e6b1
remove pc+4 piperegs and add new ex pc+4 adder
2012-02-02 13:33:27 -08:00
Andrew Waterman
01a156eb98
make # of dcache lines configurable
2012-02-01 21:11:45 -08:00
Andrew Waterman
b1bbf56b74
clean up wb->id bypass
2012-02-01 16:41:18 -08:00
Henry Cook
c5a4eaa0a1
Associative cache, boots kernel
2012-02-01 13:26:04 -08:00
Henry Cook
281abfbccb
New Mux1H constructor
2012-02-01 13:24:28 -08:00
Andrew Waterman
38c9105ea1
fix mul/div deadlock bug
...
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
2012-01-30 21:14:28 -08:00
Andrew Waterman
bd241ea237
fix when badvaddr is set
2012-01-30 17:15:42 -08:00
Andrew Waterman
a96c92f58d
enable amomin[u]/amomax[u
2012-01-26 20:45:04 -08:00
Andrew Waterman
a7999d4525
don't flush I$ unless fence.i commits
...
otherwise, we might not make forward progress.
2012-01-26 20:37:09 -08:00
Andrew Waterman
32f5f420f3
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-01-26 20:12:42 -08:00
Andrew Waterman
41855a6d47
fix missing "otherwise" in PCR file
...
this fixes timer interrupts for VLSI backend.
2012-01-26 19:33:55 -08:00
Andrew Waterman
7172ddd050
don't flush pipeline after MFPCR
2012-01-24 18:40:08 -08:00
Andrew Waterman
97c379f1d7
made I$ associative
2012-01-24 16:51:30 -08:00
Henry Cook
aa3465699b
LFSR now a util
2012-01-24 15:26:19 -08:00
Andrew Waterman
7f26fe2c44
make icache size parameterizable
2012-01-24 15:13:49 -08:00
Henry Cook
8229d65adf
Associative cache passes asm tests and bmarks with power of 2 associativities (including 1)
2012-01-24 11:41:44 -08:00
Andrew Waterman
9e6b86fe85
Fix a nasty replay bug
...
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.
Example broken code:
lw x2, 0(x2) # cache miss
beq x3, x0, somewhere # mispredicted branch
move x4, x2 # wrong-path instruction dependent on load miss
2012-01-24 03:40:01 -08:00
Andrew Waterman
06fdf79dab
fix long-latency writeback arbitration bug
2012-01-24 00:56:47 -08:00
Andrew Waterman
f1c355e3cd
check pc/effective address sign extension
2012-01-24 00:15:17 -08:00
Andrew Waterman
a5a020f97b
update chisel and remove SRAM_READ_LATENCY
2012-01-23 20:59:38 -08:00
Henry Cook
8766438bb9
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
2012-01-23 17:09:23 -08:00
Andrew Waterman
e7bf07d55e
fix AMO replay bug
2012-01-23 15:35:53 -08:00
Andrew Waterman
d59bddfbf1
fix I$ miss replay bug
2012-01-21 20:42:13 -08:00
Andrew Waterman
31c56228e2
add missing "otherwise"
2012-01-21 20:13:15 -08:00
Henry Cook
97f0852b17
DM cache with assoc-aware subunits passes all asm and bmarks
2012-01-18 17:53:26 -08:00
Henry Cook
8623d58724
split into two caches, compiles
2012-01-18 17:09:35 -08:00
Henry Cook
29ed8eb31a
More utils for nbdcache
2012-01-18 17:09:35 -08:00
Henry Cook
7e25749581
Groundwork for assoc cache implementation
2012-01-18 17:09:35 -08:00
Andrew Waterman
07f184df2f
adhere to new chisel c naming convention
2012-01-18 15:23:21 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
e4cf6391d7
fix i$ miss pathology and badvaddr bug
2012-01-17 23:47:35 -08:00
Andrew Waterman
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
Andrew Waterman
1c8f496811
fix fpga build
2012-01-13 20:04:11 -08:00
Andrew Waterman
addfe55735
add FPGA memory generator script
2012-01-13 18:19:08 -08:00
Andrew Waterman
acf3134e80
minor control logic cleanup
2012-01-12 14:19:18 -08:00
Andrew Waterman
4807d7222b
use replay to handle I$ misses
...
this eliminates a long path in the fetch stage
2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350
remove icache req_rdy signal
2012-01-11 18:27:11 -08:00
Andrew Waterman
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00
Andrew Waterman
92dda102b6
slight control logic cleanup
2012-01-11 16:56:40 -08:00
Andrew Waterman
938b142d64
require writes to memory to be uninterrupted
2012-01-03 18:41:53 -08:00
Andrew Waterman
142dfc6e07
made tohost/fromhost 64 bits wide
2012-01-03 15:09:08 -08:00
Andrew Waterman
20aee36c96
move PCR writes to WB stage
2012-01-02 15:42:39 -08:00
Andrew Waterman
3045b33460
remove second RF write port
...
load miss writebacks are treated like mul/div now.
2012-01-02 02:51:30 -08:00
Andrew Waterman
ffe23a1ee8
fix WAW hazard handling
2012-01-02 00:25:11 -08:00
Andrew Waterman
eb657dd250
reduce superfluous replays
...
we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
Andrew Waterman
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
...
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
Andrew Waterman
2f8fcebea0
remove datapath register resets resets
2012-01-01 16:09:40 -08:00
Andrew Waterman
f9160c53cf
fixes for correct verilog generation
2011-12-29 23:46:21 -08:00
Andrew Waterman
1028ff7d9b
fix multiplier bug
2011-12-29 23:45:09 -08:00
Andrew Waterman
d65e1a2eee
vlsi verilog compiles now but doesn't simulate
2011-12-20 22:08:27 -08:00
Andrew Waterman
38ea10a5f4
parameterized multiplier unrolling
2011-12-20 04:18:28 -08:00
Andrew Waterman
733fc8e65e
booth multiplier
2011-12-20 03:49:07 -08:00
Andrew Waterman
b5a8b6dc73
fix divider for RV32
2011-12-19 16:57:53 -08:00
Andrew Waterman
bcceb08373
add dummy mul_rdy signal
2011-12-17 07:30:47 -08:00