riscv/rocket-chip
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fix hit logic for amos

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This commit is contained in:
Henry Cook 2012-03-12 10:38:37 -07:00
parent 6229a33dc4
commit cbf7b13341
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/coherence.scala
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@ -147,8 +147,8 @@ trait FourStateCoherence extends CoherencePolicy {
def isHit ( cmd: Bits, state: UFix): Bool = {
val (read, write) = cpuCmdToRW(cmd)
((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
(state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
}
//TODO: do we need isPresent() for determining that a line needs to be