Howard Mao
f93872d6b4
make sure cached generator actually drives finished signal
2015-11-11 18:45:36 -08:00
Howard Mao
eeda3dd770
add README
2015-11-11 18:30:19 -08:00
Howard Mao
9482d944ca
make Uncached generator vary the alloc bit
2015-11-11 18:26:56 -08:00
Howard Mao
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Howard Mao
8a6b231b08
explicitly configure the number of requests being sent by generators
2015-11-11 14:32:19 -08:00
Howard Mao
149480411e
make sure ClientTileLinkEnqueuer uses the correct parameters
2015-11-10 16:09:19 -08:00
Howard Mao
b59ce5fed4
make sure L2 waits for outer grant before sending grant for write request
2015-11-10 16:06:14 -08:00
Howard Mao
13f62e0364
make sure generators can detect lockup
2015-11-10 14:39:56 -08:00
Howard Mao
520925c207
fix up build.sbt and add gitignore
2015-11-10 13:38:39 -08:00
Howard Mao
51f128ec74
actually use backendBuffering in front of unwrapper/converter chain
2015-11-09 11:50:18 -08:00
Howard Mao
42d3d09d7a
add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer
2015-11-09 11:49:19 -08:00
Howard Mao
7942be4e01
make sure outerTL method is idempotent
2015-11-09 11:10:02 -08:00
Andrew Waterman
59ca373146
Merge pull request #18 from jackkoenig/master
...
Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
2015-11-08 22:38:01 -08:00
jackkoenig
1e259a55da
Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
2015-11-08 21:16:31 -08:00
Yunsup Lee
df5daaa72e
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-06 23:57:42 -08:00
Andrew Waterman
2f515b2af6
Reduce critical path for fdiv valid signal
2015-11-06 23:28:31 -08:00
Henry Cook
e3efc09b5b
remove unnecessary UInt encode/decode on releaseMatches path
2015-11-05 17:20:03 -08:00
Yunsup Lee
1e772daeea
no spaces in Makefrag
2015-11-05 16:42:05 -08:00
Howard Mao
cb0c2df051
update fpga-zynq
2015-11-05 10:50:13 -08:00
Howard Mao
42e7067400
bump uncore
2015-11-05 10:49:25 -08:00
Howard Mao
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
Howard Mao
fb501e75c0
fixes for sub-block TL requests in uncore
2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89
get rid of now-unnecessary bits in MIF tag
2015-11-05 10:48:32 -08:00
Howard Mao
ba5a6af05c
correctly stripe data across memory channels in simulation
2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b
fix NSets calculation
2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd
add back decoupled NASTI connection at edge of RocketChip
2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Henry Cook
3698153535
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
2015-11-03 14:31:35 -08:00
Howard Mao
3e906c8620
shave off channel select bits in MultiChannel router
2015-11-02 22:39:50 -08:00
Howard Mao
baa2544651
Fix some more issues with narrower
2015-10-31 19:36:30 -07:00
Howard Mao
d844bee310
properly shift grant data when checking correctness
2015-10-31 18:58:05 -07:00
Howard Mao
644b66a3a8
selectively enable or disable uncached and cached generators
2015-10-31 17:43:25 -07:00
Howard Mao
bcc631f756
generate word-size requests in uncached generator
2015-10-31 17:43:08 -07:00
Howard Mao
812c5bcc55
make sure narrower can handle sub-block level requests correctly
2015-10-31 15:58:36 -07:00
Howard Mao
d4b8653002
fix too strict assertion in broadcast hub
2015-10-31 15:58:10 -07:00
Howard Mao
c1f42ce3d4
add an L1 cache request generator
2015-10-30 12:49:57 -07:00
Colin Schmidt
032bdd0601
Merge pull request #24 from ucb-bar/regression-master
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Add a "--master" flag to the regression script
2015-10-29 14:15:44 -07:00
Palmer Dabbelt
3d2a4ffdd6
Add a "--master" flag to the regression script
...
I want to be able to test the master of riscv-gnu-toolchain against the current
RTL as part of the buildbot. This flag takes a list of repositories (by their
submodule path) and updates those to the current master, which facilitates that
check.
2015-10-29 14:11:26 -07:00
Howard Mao
3103fa8da2
rename tl to mem in generator
2015-10-27 17:14:56 -07:00
Howard Mao
c10870a87c
make sure ID width requirement in TL -> NASTI converter is correct
2015-10-27 13:25:29 -07:00
Howard Mao
aeb9c86459
use the uncached port instead of the cached port
2015-10-26 23:09:36 -07:00
Howard Mao
b22088d934
make sure data checked is same as data sent
2015-10-26 21:55:04 -07:00
Howard Mao
2b252bc6ff
first commit
2015-10-26 21:43:50 -07:00
