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rocket-chip/rocket/src/main/scala/icache.scala

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Scala
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package rocket
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import Chisel._;
import Node._;
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import Constants._;
import scala.math._;
// interface between I$ and pipeline/ITLB (32 bits wide)
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class ioImem extends Bundle
{
val invalidate = Bool(INPUT);
val itlb_miss = Bool(INPUT);
val req_val = Bool(INPUT);
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val req_idx = Bits(INPUT, PGIDX_BITS);
val req_ppn = Bits(INPUT, PPN_BITS);
val resp_data = Bits(OUTPUT, 32);
val resp_val = Bool(OUTPUT);
}
class ioRocketICache extends Bundle()
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{
val cpu = new ioImem();
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val mem = new ioUncachedRequestor
}
// basic direct mapped instruction cache
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
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{
val io = new ioRocketICache();
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val lines = sets * assoc;
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val addrbits = PADDR_BITS;
val indexbits = log2Up(sets);
val offsetbits = OFFSET_BITS;
val tagmsb = addrbits - 1;
val taglsb = indexbits+offsetbits;
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val tagbits = addrbits-taglsb;
val indexmsb = taglsb-1;
val indexlsb = offsetbits;
val offsetmsb = indexlsb-1;
val databits = 32;
val offsetlsb = log2Up(databits/8);
val rf_cnt_bits = log2Up(REFILL_CYCLES);
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require(PGIDX_BITS >= taglsb); // virtually-indexed, physically-tagged constraint
require(isPow2(sets) && isPow2(assoc));
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
val state = Reg(resetVal = s_reset);
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val invalidated = Reg() { Bool() }
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val r_cpu_req_idx = Reg { Bits() }
val r_cpu_req_ppn = Reg { Bits() }
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val rdy = Bool()
val tag_hit = Bool()
when (io.cpu.req_val && rdy) {
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r_cpu_req_val := Bool(true)
r_cpu_req_idx := io.cpu.req_idx
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}
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.otherwise {
r_cpu_req_val := Bool(false)
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}
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when (state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss) {
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r_cpu_req_ppn := io.cpu.req_ppn
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}
val r_cpu_hit_addr = Cat(io.cpu.req_ppn, r_cpu_req_idx)
val r_cpu_hit_tag = r_cpu_hit_addr(tagmsb,taglsb)
val r_cpu_miss_addr = Cat(r_cpu_req_ppn, r_cpu_req_idx)
val r_cpu_miss_tag = r_cpu_miss_addr(tagmsb,taglsb)
// refill counter
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val refill_count = Reg(resetVal = UFix(0, rf_cnt_bits));
when (io.mem.xact_rep.valid) {
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refill_count := refill_count + UFix(1);
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}
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val refill_done = io.mem.xact_rep.valid && refill_count.andR
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val repl_way = if (assoc == 1) UFix(0) else LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2Up(assoc)-1,0)
val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2Up(databits))).toUFix
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val tag_we = refill_done
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val tag_addr =
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Mux((state === s_refill), r_cpu_req_idx(indexmsb,indexlsb),
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io.cpu.req_idx(indexmsb,indexlsb)).toUFix;
val data_addr =
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count),
io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix;
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val tag_array = Mem(sets, seqRead = true) { Bits(width = tagbits*assoc) }
val tag_rdata = Reg() { Bits() }
when (tag_we) {
tag_array.write(tag_addr, Fill(assoc, r_cpu_miss_tag), FillInterleaved(tagbits, if (assoc > 1) UFixToOH(repl_way) else Bits(1)))
}.otherwise {
tag_rdata := tag_array(tag_addr)
}
val vb_array = Reg(resetVal = Bits(0, lines))
when (io.cpu.invalidate) {
vb_array := Bits(0)
}.elsewhen (tag_we) {
vb_array := vb_array.bitSet(Cat(r_cpu_req_idx(indexmsb,indexlsb), if (assoc > 1) repl_way else null), !invalidated)
}
val data_mux = (new Mux1H(assoc)){Bits(width = databits)}
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var any_hit = Bool(false)
for (i <- 0 until assoc)
{
val valid = vb_array(Cat(r_cpu_req_idx(indexmsb,indexlsb), if (assoc > 1) UFix(i, log2Up(assoc)) else null))
val hit = valid && tag_rdata(tagbits*(i+1)-1, tagbits*i) === r_cpu_hit_addr(tagmsb,taglsb)
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// data array
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val data_array = Mem(sets*REFILL_CYCLES, seqRead = true){ io.mem.xact_rep.bits.data.clone }
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val data_out = Reg(){ io.mem.xact_rep.bits.data.clone }
when (io.mem.xact_rep.valid && repl_way === UFix(i)) { data_array(data_addr) := io.mem.xact_rep.bits.data }
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.otherwise { data_out := data_array(data_addr) }
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data_mux.io.sel(i) := hit
data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0);
any_hit = any_hit || hit
}
tag_hit := any_hit
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val finish_q = (new queue(1)) { new TransactionFinish }
finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.require_ack
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finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
// output signals
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_hit;
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
io.cpu.resp_data := data_mux.io.out
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io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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io.mem.xact_finish <> finish_q.io.deq
// control state machine
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when (io.cpu.invalidate) {
invalidated := Bool(true)
}
switch (state) {
is (s_reset) {
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state := s_ready;
}
is (s_ready) {
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when (r_cpu_req_val && !tag_hit && !io.cpu.itlb_miss) {
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state := s_request;
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}
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invalidated := Bool(false)
}
is (s_request)
{
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when (io.mem.xact_init.ready && finish_q.io.enq.ready) {
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state := s_refill_wait;
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}
}
is (s_refill_wait) {
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when (io.mem.xact_abort.valid) {
state := s_request
}
when (io.mem.xact_rep.valid) {
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state := s_refill;
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}
}
is (s_refill) {
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when (refill_done) {
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state := s_ready;
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}
}
}
}