2011-10-26 08:02:47 +02:00
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package Top {
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2011-11-09 23:52:17 +01:00
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import Chisel._;
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2011-10-26 08:02:47 +02:00
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import Node._;
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2011-11-09 23:52:17 +01:00
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import Constants._;
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2011-10-26 08:02:47 +02:00
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import scala.math._;
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2011-11-10 06:54:11 +01:00
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// interface between I$ and pipeline/ITLB (32 bits wide)
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2011-10-26 08:02:47 +02:00
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class ioImem(view: List[String] = null) extends Bundle (view)
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{
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2012-01-18 19:28:48 +01:00
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val invalidate = Bool(INPUT);
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val itlb_miss = Bool(INPUT);
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val req_val = Bool(INPUT);
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val req_idx = Bits(PGIDX_BITS, INPUT);
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val req_ppn = Bits(PPN_BITS, INPUT);
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val resp_data = Bits(32, OUTPUT);
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val resp_val = Bool(OUTPUT);
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2011-10-26 08:02:47 +02:00
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}
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// interface between I$ and memory (128 bits wide)
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class ioIcache(view: List[String] = null) extends Bundle (view)
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{
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2012-01-18 19:28:48 +01:00
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val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
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val resp_val = Bool(OUTPUT);
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2011-10-26 08:02:47 +02:00
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}
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2011-11-05 04:52:21 +01:00
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class ioICacheDM extends Bundle()
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{
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2011-10-26 08:02:47 +02:00
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val cpu = new ioImem();
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val mem = new ioIcache().flip();
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}
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// basic direct mapped instruction cache
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2011-11-10 09:50:09 +01:00
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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2011-10-26 08:02:47 +02:00
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// parameters :
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// lines = # cache lines
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2011-11-09 23:52:17 +01:00
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class rocketICacheDM(lines: Int) extends Component {
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2011-10-26 08:02:47 +02:00
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val io = new ioICacheDM();
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2011-11-07 09:58:25 +01:00
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2011-11-09 23:52:17 +01:00
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val addrbits = PADDR_BITS;
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2011-10-26 08:02:47 +02:00
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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2011-12-12 15:49:16 +01:00
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val offsetbits = OFFSET_BITS;
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2011-10-26 08:02:47 +02:00
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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2011-11-12 09:25:06 +01:00
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val tagbits = addrbits-taglsb;
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2011-10-26 08:02:47 +02:00
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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2011-11-07 09:58:25 +01:00
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val databits = 32;
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2011-12-09 09:42:43 +01:00
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val offsetlsb = ceil(log(databits/8)/log(2)).toInt;
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val rf_cnt_bits = ceil(log(REFILL_CYCLES)/log(2)).toInt;
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2011-10-26 08:02:47 +02:00
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2012-01-12 03:27:11 +01:00
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
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2011-10-26 08:02:47 +02:00
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val state = Reg(resetVal = s_reset);
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2011-12-12 15:49:16 +01:00
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val r_cpu_req_idx = Reg { Bits(width = PGIDX_BITS) }
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val r_cpu_req_ppn = Reg { Bits(width = PPN_BITS) }
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2011-11-12 09:25:06 +01:00
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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2012-01-12 04:20:20 +01:00
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val rdy = Wire() { Bool() }
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2011-10-26 08:02:47 +02:00
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2012-01-12 04:20:20 +01:00
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when (io.cpu.req_val && rdy) {
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2011-11-12 09:25:06 +01:00
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r_cpu_req_idx <== io.cpu.req_idx;
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}
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2011-11-13 00:00:45 +01:00
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when (state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss) {
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2011-11-12 09:25:06 +01:00
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r_cpu_req_ppn <== io.cpu.req_ppn;
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}
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2012-01-12 04:20:20 +01:00
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when (rdy) {
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2011-11-12 09:25:06 +01:00
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r_cpu_req_val <== io.cpu.req_val;
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2011-11-05 04:52:21 +01:00
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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2011-10-26 08:02:47 +02:00
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2011-11-13 07:13:29 +01:00
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// refill counter
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2011-12-09 09:42:43 +01:00
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val refill_count = Reg(resetVal = UFix(0, rf_cnt_bits));
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2011-11-05 04:52:21 +01:00
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when (io.mem.resp_val) {
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refill_count <== refill_count + UFix(1);
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}
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2011-11-12 09:25:06 +01:00
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val tag_addr =
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Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits),
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io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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val tag_we = (state === s_refill_wait) && io.mem.resp_val;
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2011-12-04 04:41:15 +01:00
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val tag_array = Mem4(lines, r_cpu_req_ppn);
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2012-01-24 05:59:38 +01:00
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tag_array.setReadLatency(1);
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2012-01-14 03:18:48 +01:00
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tag_array.setTarget('inst);
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2011-12-04 04:41:15 +01:00
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val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
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2011-12-04 10:18:38 +01:00
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2011-10-26 08:02:47 +02:00
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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2011-11-14 13:13:13 +01:00
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when (io.cpu.invalidate) {
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vb_array <== Bits(0,lines);
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}
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2011-11-12 09:25:06 +01:00
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when (tag_we) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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2011-11-05 04:52:21 +01:00
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}
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2011-10-26 08:02:47 +02:00
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2011-11-12 09:25:06 +01:00
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val tag_valid = Reg(vb_array(tag_addr)).toBool;
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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2011-10-26 08:02:47 +02:00
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// data array
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2011-12-04 04:41:15 +01:00
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val data_addr =
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2011-11-12 09:25:06 +01:00
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
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2011-12-09 09:42:43 +01:00
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val data_array = Mem4(lines*REFILL_CYCLES, io.mem.resp_data);
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2012-01-24 05:59:38 +01:00
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data_array.setReadLatency(1);
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2012-01-14 03:18:48 +01:00
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data_array.setTarget('inst);
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2011-12-04 04:41:15 +01:00
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val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
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2011-11-07 09:58:25 +01:00
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// output signals
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2012-01-12 04:20:20 +01:00
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && Reg(rdy) && r_cpu_req_val && tag_valid && tag_match;
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rdy <== !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match));
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2011-12-17 12:26:11 +01:00
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io.cpu.resp_data := data_array_rdata >> Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
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2011-10-26 08:02:47 +02:00
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io.mem.req_val := (state === s_request);
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2011-12-12 15:49:16 +01:00
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io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(indexmsb,indexlsb)).toUFix
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2011-10-26 08:02:47 +02:00
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// control state machine
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switch (state) {
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is (s_reset) {
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state <== s_ready;
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}
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is (s_ready) {
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2011-11-13 00:00:45 +01:00
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when (io.cpu.itlb_miss) {
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state <== s_ready;
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}
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when (r_cpu_req_val && !(tag_valid && tag_match)) {
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state <== s_request;
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}
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2011-10-26 08:02:47 +02:00
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}
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is (s_request)
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{
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2011-11-12 09:25:06 +01:00
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when (io.mem.req_rdy) {
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state <== s_refill_wait;
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}
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2011-10-26 08:02:47 +02:00
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}
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is (s_refill_wait) {
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2011-11-12 09:25:06 +01:00
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when (io.mem.resp_val) {
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state <== s_refill;
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}
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2011-10-26 08:02:47 +02:00
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}
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is (s_refill) {
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2011-12-09 09:42:43 +01:00
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when (io.mem.resp_val && (~refill_count === UFix(0))) {
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2012-01-12 03:27:11 +01:00
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state <== s_ready;
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2011-11-12 09:25:06 +01:00
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}
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2011-10-26 08:02:47 +02:00
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}
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}
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}
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}
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