2014-09-13 03:06:41 +02:00
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// See LICENSE for license details.
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2014-03-25 13:22:04 +01:00
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package rocket
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import Chisel._
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2015-07-30 02:22:22 +02:00
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import junctions._
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2015-10-22 03:18:32 +02:00
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import cde.{Parameters, Field}
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2014-03-25 13:22:04 +01:00
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import Util._
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2015-10-06 06:48:05 +02:00
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case object BtbKey extends Field[BtbParameters]
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2015-10-17 04:11:57 +02:00
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case class BtbParameters(
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enabled: Boolean = true,
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nEntries: Int = 62,
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nRAS: Int = 2,
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updatesOutOfOrder: Boolean = false)
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2015-10-06 06:48:05 +02:00
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abstract trait HasBtbParameters extends HasCoreParameters {
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2015-10-07 03:20:19 +02:00
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val matchBits = pgIdxBits
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2015-10-06 06:48:05 +02:00
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val entries = p(BtbKey).nEntries
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val nRAS = p(BtbKey).nRAS
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val updatesOutOfOrder = p(BtbKey).updatesOutOfOrder
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2014-08-12 03:36:23 +02:00
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val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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2014-04-08 00:58:49 +02:00
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2015-10-06 06:48:05 +02:00
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abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
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abstract class BtbBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasBtbParameters
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2014-08-08 21:23:02 +02:00
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class RAS(nras: Int) {
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2014-04-08 00:58:49 +02:00
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def push(addr: UInt): Unit = {
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2014-08-08 21:23:02 +02:00
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when (count < nras) { count := count + 1 }
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2015-01-30 00:29:25 +01:00
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val nextPos = Mux(Bool(isPow2(nras)) || pos < nras-1, pos+1, UInt(0))
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2014-04-08 00:58:49 +02:00
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stack(nextPos) := addr
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pos := nextPos
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}
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def peek: UInt = stack(pos)
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def pop: Unit = when (!isEmpty) {
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count := count - 1
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2014-08-08 21:23:02 +02:00
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pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
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2014-04-08 00:58:49 +02:00
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}
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def clear: Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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2014-08-08 21:23:02 +02:00
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private val count = Reg(init=UInt(0,log2Up(nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(nras)))
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2016-01-14 22:57:45 +01:00
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private val stack = Reg(Vec(nras, UInt()))
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2014-04-08 00:58:49 +02:00
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}
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2015-10-06 06:48:05 +02:00
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class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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2014-09-20 00:05:45 +02:00
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val history = UInt(width = log2Up(nBHT).max(1))
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2014-04-08 00:58:49 +02:00
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val value = UInt(width = 2)
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}
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2014-10-03 13:22:58 +02:00
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// BHT contains table of 2-bit counters and a global history register.
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// The BHT only predicts and updates when there is a BTB hit.
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// The global history:
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// - updated speculatively in fetch (if there's a BTB hit).
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// - on a mispredict, the history register is reset (again, only if BTB hit).
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// The counter table:
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2014-11-17 07:02:27 +01:00
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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2014-10-04 01:08:08 +02:00
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// - updated when a branch resolves (and BTB was a hit for that branch).
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2014-10-15 03:10:29 +02:00
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// The updating branch must provide its "fetch pc".
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2015-10-06 06:48:05 +02:00
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class BHT(nbht: Int)(implicit p: Parameters) {
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2014-09-26 19:39:57 +02:00
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val nbhtbits = log2Up(nbht)
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2014-09-30 06:41:07 +02:00
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def get(addr: UInt, update: Bool): BHTResp = {
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2015-07-16 05:24:18 +02:00
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val res = Wire(new BHTResp)
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2014-10-04 01:08:08 +02:00
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val index = addr(nbhtbits+1,2) ^ history
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res.value := table(index)
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2014-09-28 14:16:36 +02:00
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res.history := history
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2014-09-30 06:41:07 +02:00
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val taken = res.value(0)
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when (update) { history := Cat(taken, history(nbhtbits-1,1)) }
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2014-04-08 00:58:49 +02:00
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res
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}
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2014-11-17 07:02:27 +01:00
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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2014-10-04 01:08:08 +02:00
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val index = addr(nbhtbits+1,2) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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2014-11-17 07:02:27 +01:00
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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2014-04-08 00:58:49 +02:00
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}
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2015-09-30 23:36:26 +02:00
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private val table = Mem(nbht, UInt(width = 2))
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2014-08-08 21:23:02 +02:00
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val history = Reg(UInt(width = nbhtbits))
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2014-04-02 00:01:27 +02:00
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}
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2014-11-11 12:34:05 +01:00
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// BTB update occurs during branch resolution (and only on a mispredict).
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2014-09-17 23:24:03 +02:00
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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2015-10-06 06:48:05 +02:00
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class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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2014-04-02 00:01:27 +02:00
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val prediction = Valid(new BTBResp)
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2014-08-12 03:36:23 +02:00
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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2014-04-02 00:01:27 +02:00
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val taken = Bool()
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2014-04-08 00:58:49 +02:00
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val isJump = Bool()
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2014-04-02 00:01:27 +02:00
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val isReturn = Bool()
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2014-09-17 23:24:03 +02:00
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val br_pc = UInt(width = vaddrBits)
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2014-04-02 00:01:27 +02:00
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}
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2014-11-17 07:02:27 +01:00
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// BHT update occurs during branch resolution on all conditional branches.
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// - "pc" is what future fetch PCs will tag match against.
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2015-10-06 06:48:05 +02:00
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class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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2014-11-17 07:02:27 +01:00
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val taken = Bool()
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val mispredict = Bool()
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}
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2015-10-06 06:48:05 +02:00
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class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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2014-11-11 12:34:05 +01:00
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val isCall = Bool()
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val isReturn = Bool()
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val returnAddr = UInt(width = vaddrBits)
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val prediction = Valid(new BTBResp)
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}
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// - "bridx" is the low-order PC bits of the predicted branch (after
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2014-11-17 07:02:27 +01:00
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// shifting off the lowest log(inst_bytes) bits off).
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2014-11-11 12:34:05 +01:00
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// - "resp.mask" provides a mask of valid instructions (instructions are
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2014-11-17 07:02:27 +01:00
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// masked off by the predicted taken branch).
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2015-10-06 06:48:05 +02:00
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class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
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2014-04-02 00:01:27 +02:00
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val taken = Bool()
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2015-10-06 06:48:05 +02:00
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val mask = Bits(width = fetchWidth)
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val bridx = Bits(width = log2Up(fetchWidth))
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2014-08-12 03:36:23 +02:00
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val target = UInt(width = vaddrBits)
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val entry = UInt(width = opaqueBits)
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2014-04-08 00:58:49 +02:00
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val bht = new BHTResp
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2014-04-02 00:01:27 +02:00
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}
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2015-10-06 06:48:05 +02:00
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class BTBReq(implicit p: Parameters) extends BtbBundle()(p) {
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2014-09-30 06:41:07 +02:00
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val addr = UInt(width = vaddrBits)
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}
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2014-03-25 13:22:04 +01:00
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// fully-associative branch target buffer
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2014-11-11 12:34:05 +01:00
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// Higher-performance processors may cause BTB updates to occur out-of-order,
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// which requires an extra CAM port for updates (to ensure no duplicates get
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// placed in BTB).
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2015-10-06 06:48:05 +02:00
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class BTB(implicit p: Parameters) extends BtbModule {
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2014-03-25 13:22:04 +01:00
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val io = new Bundle {
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2014-09-30 06:41:07 +02:00
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val req = Valid(new BTBReq).flip
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2014-04-02 00:01:27 +02:00
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val resp = Valid(new BTBResp)
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2014-11-17 07:02:27 +01:00
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val btb_update = Valid(new BTBUpdate).flip
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val bht_update = Valid(new BHTUpdate).flip
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2014-11-11 12:34:05 +01:00
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val ras_update = Valid(new RASUpdate).flip
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2014-04-02 00:01:27 +02:00
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val invalidate = Bool(INPUT)
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2014-03-25 13:22:04 +01:00
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}
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2015-07-31 13:59:45 +02:00
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val idxValid = Reg(init=UInt(0, entries))
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2015-09-30 23:36:26 +02:00
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val idxs = Mem(entries, UInt(width=matchBits))
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val idxPages = Mem(entries, UInt(width=log2Up(nPages)))
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val tgts = Mem(entries, UInt(width=matchBits))
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val tgtPages = Mem(entries, UInt(width=log2Up(nPages)))
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val pages = Mem(nPages, UInt(width=vaddrBits-matchBits))
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2014-08-12 03:36:23 +02:00
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val pageValid = Reg(init=UInt(0, nPages))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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2014-04-02 00:01:27 +02:00
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2015-09-30 23:36:26 +02:00
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val useRAS = Reg(Vec(entries, Bool()))
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val isJump = Reg(Vec(entries, Bool()))
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2015-10-06 06:48:05 +02:00
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val brIdx = Mem(entries, UInt(width=log2Up(fetchWidth)))
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2014-03-25 13:22:04 +01:00
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2014-08-12 03:36:23 +02:00
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private def page(addr: UInt) = addr >> matchBits
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2014-03-25 13:22:04 +01:00
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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2014-05-19 04:25:43 +02:00
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Vec(pages.map(_ === p)).toBits & pageValid
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2014-03-25 13:22:04 +01:00
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}
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2015-07-31 13:59:45 +02:00
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private def tagMatch(addr: UInt, pgMatch: UInt) = {
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2014-08-12 03:36:23 +02:00
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val idx = addr(matchBits-1,0)
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2014-03-25 13:22:04 +01:00
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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2015-07-31 13:59:45 +02:00
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idxValid & idxMatch & idxPageMatch
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2014-03-25 13:22:04 +01:00
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}
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2014-11-17 07:02:27 +01:00
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val r_btb_update = Pipe(io.btb_update)
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2014-09-30 06:41:07 +02:00
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val update_target = io.req.bits.addr
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2014-04-02 00:01:27 +02:00
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2014-09-30 06:41:07 +02:00
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val pageHit = pageMatch(io.req.bits.addr)
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val hits = tagMatch(io.req.bits.addr, pageHit)
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2014-11-17 07:02:27 +01:00
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val updatePageHit = pageMatch(r_btb_update.bits.pc)
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val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit)
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2014-03-25 13:22:04 +01:00
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2014-11-17 07:02:27 +01:00
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private var lfsr = LFSR16(r_btb_update.valid)
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2014-03-25 13:22:04 +01:00
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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2014-11-17 07:02:27 +01:00
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val updateHit = r_btb_update.bits.prediction.valid
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2015-09-30 21:43:00 +02:00
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val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
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2014-03-25 13:22:04 +01:00
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2014-04-02 00:01:27 +02:00
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val useUpdatePageHit = updatePageHit.orR
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2014-11-17 07:02:27 +01:00
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val doIdxPageRepl = !useUpdatePageHit
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2015-07-31 23:23:52 +02:00
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val idxPageRepl = Wire(UInt(width = nPages))
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2014-04-08 00:58:49 +02:00
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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2014-03-25 13:22:04 +01:00
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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2014-11-17 07:02:27 +01:00
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val samePage = page(r_btb_update.bits.pc) === page(update_target)
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2014-04-02 00:01:27 +02:00
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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2014-11-17 07:02:27 +01:00
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val doTgtPageRepl = !samePage && !usePageHit
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2014-08-12 03:36:23 +02:00
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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2014-04-08 00:58:49 +02:00
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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2014-03-25 13:22:04 +01:00
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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2014-05-19 04:25:43 +02:00
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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2014-03-25 13:22:04 +01:00
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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2014-11-17 07:02:27 +01:00
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idxPageRepl := UIntToOH(Counter(r_btb_update.valid && doPageRepl, nPages)._1)
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2014-04-08 00:58:49 +02:00
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2014-11-17 07:02:27 +01:00
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when (r_btb_update.valid) {
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assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
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2014-11-11 12:34:05 +01:00
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2014-11-17 07:02:27 +01:00
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val waddr =
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2015-10-06 06:48:05 +02:00
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if (updatesOutOfOrder) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
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2014-11-17 07:02:27 +01:00
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else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)
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2014-03-25 13:22:04 +01:00
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2014-05-20 03:56:30 +02:00
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// invalidate entries if we stomp on pages they depend upon
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2015-07-31 13:59:45 +02:00
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val invalidateMask = Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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val validateMask = UIntToOH(waddr)
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idxValid := (idxValid & ~invalidateMask) | validateMask
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2014-05-20 03:56:30 +02:00
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2014-11-17 07:02:27 +01:00
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idxs(waddr) := r_btb_update.bits.pc
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2014-11-11 12:34:05 +01:00
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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2014-11-17 07:02:27 +01:00
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useRAS(waddr) := r_btb_update.bits.isReturn
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isJump(waddr) := r_btb_update.bits.isJump
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2015-10-06 06:48:05 +02:00
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if (fetchWidth == 1) {
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2014-11-11 12:34:05 +01:00
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brIdx(waddr) := UInt(0)
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} else {
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2015-10-06 06:48:05 +02:00
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brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes)
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2014-03-25 13:22:04 +01:00
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}
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2014-08-12 03:36:23 +02:00
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require(nPages % 2 == 0)
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val idxWritesEven = (idxPageUpdateOH & Fill(nPages/2, UInt(1,2))).orR
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2014-03-25 13:22:04 +01:00
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2014-05-19 04:25:43 +02:00
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
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2014-08-12 03:36:23 +02:00
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for (i <- i until nPages by mod)
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2014-05-19 04:25:43 +02:00
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when (en && pageReplEn(i)) { pages(i) := data }
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2014-03-25 13:22:04 +01:00
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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2014-11-17 07:02:27 +01:00
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Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))
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2014-03-25 13:22:04 +01:00
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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2014-11-17 07:02:27 +01:00
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Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))
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2014-05-19 04:25:43 +02:00
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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2014-03-25 13:22:04 +01:00
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}
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when (io.invalidate) {
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2014-05-19 04:25:43 +02:00
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idxValid := 0
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pageValid := 0
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2014-03-25 13:22:04 +01:00
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}
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2015-07-31 13:59:45 +02:00
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io.resp.valid := hits.orR
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2014-04-02 00:01:27 +02:00
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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2014-04-08 00:58:49 +02:00
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io.resp.bits.entry := OHToUInt(hits)
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2014-10-04 01:08:08 +02:00
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io.resp.bits.bridx := brIdx(io.resp.bits.entry)
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2015-10-06 06:48:05 +02:00
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if (fetchWidth == 1) {
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2014-10-21 03:45:23 +02:00
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io.resp.bits.mask := UInt(1)
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} else {
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2014-11-03 10:13:22 +01:00
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// note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
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2014-11-11 12:34:05 +01:00
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io.resp.bits.mask := Mux(io.resp.bits.taken, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
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2014-11-17 07:02:27 +01:00
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SInt(-1))
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2014-10-21 03:45:23 +02:00
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}
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2014-04-08 00:58:49 +02:00
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2014-08-12 03:36:23 +02:00
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if (nBHT > 0) {
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2014-10-04 01:08:08 +02:00
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val bht = new BHT(nBHT)
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2015-07-30 00:03:01 +02:00
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val isBranch = !Mux1H(hits, isJump)
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val res = bht.get(io.req.bits.addr, io.req.valid && io.resp.valid && isBranch)
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2014-11-17 07:02:27 +01:00
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict)
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2014-09-26 19:39:57 +02:00
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}
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2015-07-30 00:03:01 +02:00
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when (!res.value(0) && isBranch) { io.resp.bits.taken := false }
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2014-04-08 00:58:49 +02:00
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io.resp.bits.bht := res
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}
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2014-04-02 00:01:27 +02:00
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2014-08-12 03:36:23 +02:00
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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2014-04-08 08:47:53 +02:00
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val doPeek = Mux1H(hits, useRAS)
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when (!ras.isEmpty && doPeek) {
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2014-04-08 00:58:49 +02:00
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io.resp.bits.target := ras.peek
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2014-04-02 00:01:27 +02:00
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}
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2014-11-11 12:34:05 +01:00
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when (io.ras_update.valid) {
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when (io.ras_update.bits.isCall) {
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ras.push(io.ras_update.bits.returnAddr)
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2014-04-08 08:47:53 +02:00
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when (doPeek) {
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2014-11-11 12:34:05 +01:00
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io.resp.bits.target := io.ras_update.bits.returnAddr
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2014-04-08 08:47:53 +02:00
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}
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2014-11-11 12:34:05 +01:00
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}.elsewhen (io.ras_update.bits.isReturn && io.ras_update.bits.prediction.valid) {
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2014-04-08 00:58:49 +02:00
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ras.pop
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}
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2014-04-02 00:01:27 +02:00
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}
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when (io.invalidate) { ras.clear }
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}
|
2014-03-25 13:22:04 +01:00
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}
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