2014-09-13 03:06:41 +02:00
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// See LICENSE for license details.
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2014-03-25 13:22:04 +01:00
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package rocket
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import Chisel._
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import Util._
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import Node._
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2014-08-08 21:23:02 +02:00
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import uncore._
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2014-03-25 13:22:04 +01:00
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2014-09-01 22:28:58 +02:00
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case object NBTBEntries extends Field[Int]
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2014-09-26 19:39:57 +02:00
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case object NRAS extends Field[Int]
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2014-08-12 03:36:23 +02:00
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abstract trait BTBParameters extends UsesParameters {
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val vaddrBits = params(VAddrBits)
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val matchBits = params(PgIdxBits)
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2014-09-01 22:28:58 +02:00
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val entries = params(NBTBEntries)
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2014-08-12 03:36:23 +02:00
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val nRAS = params(NRAS)
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val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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2014-04-08 00:58:49 +02:00
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2014-08-08 21:23:02 +02:00
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class RAS(nras: Int) {
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2014-04-08 00:58:49 +02:00
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def push(addr: UInt): Unit = {
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2014-08-08 21:23:02 +02:00
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when (count < nras) { count := count + 1 }
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val nextPos = Mux(Bool(isPow2(nras)) || pos > 0, pos+1, UInt(0))
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2014-04-08 00:58:49 +02:00
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stack(nextPos) := addr
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pos := nextPos
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}
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def peek: UInt = stack(pos)
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def pop: Unit = when (!isEmpty) {
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count := count - 1
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2014-08-08 21:23:02 +02:00
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pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
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2014-04-08 00:58:49 +02:00
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}
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def clear: Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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2014-08-08 21:23:02 +02:00
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private val count = Reg(init=UInt(0,log2Up(nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(nras)))
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private val stack = Vec.fill(nras){Reg(UInt())}
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2014-04-08 00:58:49 +02:00
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}
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2014-08-12 03:36:23 +02:00
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class BHTResp extends Bundle with BTBParameters {
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2014-09-20 00:05:45 +02:00
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val history = UInt(width = log2Up(nBHT).max(1))
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2014-04-08 00:58:49 +02:00
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val value = UInt(width = 2)
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}
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2014-10-03 13:22:58 +02:00
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// BHT contains table of 2-bit counters and a global history register.
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// The BHT only predicts and updates when there is a BTB hit.
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// The global history:
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// - updated speculatively in fetch (if there's a BTB hit).
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// - on a mispredict, the history register is reset (again, only if BTB hit).
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// The counter table:
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// - each PC has its own counter, updated when a branch resolves (and BTB hit).
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// - the BTB provides the predicted branch PC, allowing us to properly index
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// the counter table and provide the prediction for that specific branch.
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// Critical path concerns may require only providing a single counter for
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// the entire fetch packet, but that complicates how multiple branches
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// update that line.
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class BHT(nbht: Int, fetchwidth: Int) {
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2014-09-26 19:39:57 +02:00
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val nbhtbits = log2Up(nbht)
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2014-10-03 13:22:58 +02:00
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private val logfw = if (fetchwidth == 1) 0 else log2Up(fetchwidth)
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def get(fetch_addr: UInt, bridx: UInt, update: Bool): BHTResp = {
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2014-04-08 00:58:49 +02:00
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val res = new BHTResp
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2014-10-03 13:22:58 +02:00
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val aligned_addr = fetch_addr >> UInt(logfw + 2)
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val index = aligned_addr ^ history
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val counters = table(index)
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res.value := (counters >> (bridx<<1)) & Bits(0x3)
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2014-09-28 14:16:36 +02:00
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res.history := history
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2014-09-30 06:41:07 +02:00
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val taken = res.value(0)
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when (update) { history := Cat(taken, history(nbhtbits-1,1)) }
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2014-04-08 00:58:49 +02:00
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res
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}
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2014-09-26 19:39:57 +02:00
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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2014-10-03 13:22:58 +02:00
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val aligned_addr = addr >> UInt(logfw + 2)
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val index = aligned_addr ^ d.history
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val new_cntr = Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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var bridx: UInt = null
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if (logfw == 0) bridx = UInt(0) else bridx = addr(logfw+1,2)
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val mask = Bits(0x3) << (bridx<<1)
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table.write(index, new_cntr, mask)
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2014-09-30 06:41:07 +02:00
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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2014-04-08 00:58:49 +02:00
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}
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2014-10-03 13:22:58 +02:00
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private val table = Mem(UInt(width = 2*fetchwidth), nbht)
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2014-08-08 21:23:02 +02:00
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val history = Reg(UInt(width = nbhtbits))
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2014-04-02 00:01:27 +02:00
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}
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2014-10-03 13:22:58 +02:00
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// BTB update occurs during branch resolution.
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2014-09-17 23:24:03 +02:00
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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// - "resp.mask" provides a mask of valid instructions (instructions are
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2014-10-03 13:22:58 +02:00
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// masked off by the predicted taken branch).
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2014-08-12 03:36:23 +02:00
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class BTBUpdate extends Bundle with BTBParameters {
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2014-04-02 00:01:27 +02:00
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val prediction = Valid(new BTBResp)
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2014-08-12 03:36:23 +02:00
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val returnAddr = UInt(width = vaddrBits)
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2014-04-02 00:01:27 +02:00
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val taken = Bool()
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2014-04-08 00:58:49 +02:00
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val isJump = Bool()
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2014-04-02 00:01:27 +02:00
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val isCall = Bool()
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val isReturn = Bool()
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2014-09-17 23:24:03 +02:00
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val br_pc = UInt(width = vaddrBits)
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2014-04-02 00:01:27 +02:00
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val incorrectTarget = Bool()
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}
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2014-08-12 03:36:23 +02:00
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class BTBResp extends Bundle with BTBParameters {
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2014-04-02 00:01:27 +02:00
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val taken = Bool()
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2014-09-17 23:24:03 +02:00
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val mask = Bits(width = log2Up(params(FetchWidth)))
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2014-08-12 03:36:23 +02:00
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val target = UInt(width = vaddrBits)
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val entry = UInt(width = opaqueBits)
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2014-04-08 00:58:49 +02:00
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val bht = new BHTResp
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2014-04-02 00:01:27 +02:00
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}
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2014-09-30 06:41:07 +02:00
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class BTBReq extends Bundle with BTBParameters {
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val addr = UInt(width = vaddrBits)
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}
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2014-03-25 13:22:04 +01:00
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// fully-associative branch target buffer
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2014-08-12 03:36:23 +02:00
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class BTB extends Module with BTBParameters {
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2014-03-25 13:22:04 +01:00
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val io = new Bundle {
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2014-09-30 06:41:07 +02:00
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val req = Valid(new BTBReq).flip
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2014-04-02 00:01:27 +02:00
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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2014-03-25 13:22:04 +01:00
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}
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2014-08-12 03:36:23 +02:00
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val idxValid = Reg(init=UInt(0, entries))
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val idxs = Mem(UInt(width=matchBits), entries)
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val idxPages = Mem(UInt(width=log2Up(nPages)), entries)
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val tgts = Mem(UInt(width=matchBits), entries)
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val tgtPages = Mem(UInt(width=log2Up(nPages)), entries)
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val pages = Mem(UInt(width=vaddrBits-matchBits), nPages)
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val pageValid = Reg(init=UInt(0, nPages))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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2014-04-02 00:01:27 +02:00
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2014-08-12 03:36:23 +02:00
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val useRAS = Reg(UInt(width = entries))
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val isJump = Reg(UInt(width = entries))
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2014-09-17 23:24:03 +02:00
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val brIdx = Mem(UInt(width=log2Up(params(FetchWidth))), entries)
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2014-03-25 13:22:04 +01:00
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2014-08-12 03:36:23 +02:00
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private def page(addr: UInt) = addr >> matchBits
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2014-03-25 13:22:04 +01:00
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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2014-05-19 04:25:43 +02:00
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Vec(pages.map(_ === p)).toBits & pageValid
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2014-03-25 13:22:04 +01:00
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}
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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2014-08-12 03:36:23 +02:00
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val idx = addr(matchBits-1,0)
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2014-03-25 13:22:04 +01:00
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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2014-05-19 04:25:43 +02:00
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idxValid & idxMatch & idxPageMatch
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2014-03-25 13:22:04 +01:00
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}
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2014-09-30 06:41:07 +02:00
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val r_update = Pipe(io.update)
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val update_target = io.req.bits.addr
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2014-04-02 00:01:27 +02:00
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2014-09-30 06:41:07 +02:00
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val pageHit = pageMatch(io.req.bits.addr)
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val hits = tagMatch(io.req.bits.addr, pageHit)
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val updatePageHit = pageMatch(r_update.bits.pc)
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val updateHits = tagMatch(r_update.bits.pc, updatePageHit)
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2014-03-25 13:22:04 +01:00
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2014-09-30 06:41:07 +02:00
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private var lfsr = LFSR16(r_update.valid)
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2014-03-25 13:22:04 +01:00
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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2014-09-30 06:41:07 +02:00
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val updateHit = r_update.bits.prediction.valid
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val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && r_update.bits.incorrectTarget
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2014-03-25 13:22:04 +01:00
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2014-04-02 00:01:27 +02:00
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val useUpdatePageHit = updatePageHit.orR
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2014-04-08 00:58:49 +02:00
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
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val idxPageRepl = UInt()
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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2014-03-25 13:22:04 +01:00
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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2014-09-30 06:41:07 +02:00
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val samePage = page(r_update.bits.pc) === page(update_target)
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2014-04-02 00:01:27 +02:00
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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2014-04-08 00:58:49 +02:00
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
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2014-08-12 03:36:23 +02:00
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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2014-04-08 00:58:49 +02:00
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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2014-03-25 13:22:04 +01:00
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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2014-05-19 04:25:43 +02:00
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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2014-03-25 13:22:04 +01:00
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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2014-09-30 06:41:07 +02:00
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idxPageRepl := UIntToOH(Counter(r_update.valid && doPageRepl, nPages)._1)
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2014-04-08 00:58:49 +02:00
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2014-09-30 06:41:07 +02:00
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when (r_update.valid && !(updateValid && !updateTarget)) {
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2014-08-12 03:36:23 +02:00
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val nextRepl = Counter(!updateHit && updateValid, entries)._1
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2014-09-30 06:41:07 +02:00
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val waddr = Mux(updateHit, r_update.bits.prediction.bits.entry, nextRepl)
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2014-03-25 13:22:04 +01:00
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2014-05-20 03:56:30 +02:00
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// invalidate entries if we stomp on pages they depend upon
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2014-08-12 03:36:23 +02:00
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idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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2014-05-20 03:56:30 +02:00
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idxValid(waddr) := updateValid
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2014-05-19 04:25:43 +02:00
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when (updateTarget) {
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2014-09-30 06:41:07 +02:00
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assert(io.req.bits.addr === r_update.bits.target, "BTB request != I$ target")
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idxs(waddr) := r_update.bits.pc
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2014-05-19 04:25:43 +02:00
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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2014-09-30 06:41:07 +02:00
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useRAS(waddr) := r_update.bits.isReturn
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isJump(waddr) := r_update.bits.isJump
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2014-10-03 13:22:58 +02:00
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brIdx(waddr) := r_update.bits.br_pc
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2014-03-25 13:22:04 +01:00
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}
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2014-08-12 03:36:23 +02:00
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require(nPages % 2 == 0)
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val idxWritesEven = (idxPageUpdateOH & Fill(nPages/2, UInt(1,2))).orR
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2014-03-25 13:22:04 +01:00
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2014-05-19 04:25:43 +02:00
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
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2014-08-12 03:36:23 +02:00
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for (i <- i until nPages by mod)
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2014-05-19 04:25:43 +02:00
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when (en && pageReplEn(i)) { pages(i) := data }
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2014-03-25 13:22:04 +01:00
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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2014-09-30 06:41:07 +02:00
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Mux(idxWritesEven, page(r_update.bits.pc), page(update_target)))
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2014-03-25 13:22:04 +01:00
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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2014-09-30 06:41:07 +02:00
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Mux(idxWritesEven, page(update_target), page(r_update.bits.pc)))
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2014-05-19 04:25:43 +02:00
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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2014-03-25 13:22:04 +01:00
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}
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when (io.invalidate) {
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2014-05-19 04:25:43 +02:00
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idxValid := 0
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pageValid := 0
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2014-03-25 13:22:04 +01:00
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}
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2014-05-26 08:58:25 +02:00
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io.resp.valid := hits.orR
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2014-04-02 00:01:27 +02:00
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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2014-04-08 00:58:49 +02:00
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io.resp.bits.entry := OHToUInt(hits)
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2014-09-17 23:24:03 +02:00
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io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1))
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2014-04-08 00:58:49 +02:00
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2014-08-12 03:36:23 +02:00
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if (nBHT > 0) {
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2014-10-03 13:22:58 +02:00
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val bht = new BHT(nBHT, params(FetchWidth))
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val res = bht.get(io.req.bits.addr, brIdx(io.resp.bits.entry), io.req.valid && hits.orR && !Mux1H(hits, isJump))
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2014-09-30 06:41:07 +02:00
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val update_btb_hit = io.update.bits.prediction.valid
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when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
|
2014-10-03 13:22:58 +02:00
|
|
|
bht.update(io.update.bits.br_pc, io.update.bits.prediction.bits.bht,
|
2014-09-30 06:41:07 +02:00
|
|
|
io.update.bits.taken, io.update.bits.incorrectTarget)
|
2014-09-26 19:39:57 +02:00
|
|
|
}
|
2014-04-08 00:58:49 +02:00
|
|
|
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
|
|
|
|
io.resp.bits.bht := res
|
|
|
|
}
|
2014-04-02 00:01:27 +02:00
|
|
|
|
2014-08-12 03:36:23 +02:00
|
|
|
if (nRAS > 0) {
|
|
|
|
val ras = new RAS(nRAS)
|
2014-04-08 08:47:53 +02:00
|
|
|
val doPeek = Mux1H(hits, useRAS)
|
|
|
|
when (!ras.isEmpty && doPeek) {
|
2014-04-08 00:58:49 +02:00
|
|
|
io.resp.bits.target := ras.peek
|
2014-04-02 00:01:27 +02:00
|
|
|
}
|
2014-04-08 00:58:49 +02:00
|
|
|
when (io.update.valid) {
|
|
|
|
when (io.update.bits.isCall) {
|
|
|
|
ras.push(io.update.bits.returnAddr)
|
2014-04-08 08:47:53 +02:00
|
|
|
when (doPeek) {
|
|
|
|
io.resp.bits.target := io.update.bits.returnAddr
|
|
|
|
}
|
2014-04-08 00:58:49 +02:00
|
|
|
}.elsewhen (io.update.bits.isReturn && io.update.bits.prediction.valid) {
|
|
|
|
ras.pop
|
|
|
|
}
|
2014-04-02 00:01:27 +02:00
|
|
|
}
|
|
|
|
when (io.invalidate) { ras.clear }
|
|
|
|
}
|
2014-03-25 13:22:04 +01:00
|
|
|
}
|