122 lines
4.4 KiB
Scala
122 lines
4.4 KiB
Scala
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package rocket
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import Chisel._
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import Util._
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import Node._
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import uncore.constants.AddressConstants._
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case class BTBConfig(entries: Int) {
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val matchBits = PGIDX_BITS
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val pages0 = 1 + log2Up(entries) // is this sensible? what about matchBits?
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val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
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}
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// fully-associative branch target buffer
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class BTB(conf: BTBConfig) extends Module {
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val io = new Bundle {
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val current_pc = UInt(INPUT, VADDR_BITS)
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val hit = Bool(OUTPUT)
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val target = UInt(OUTPUT, VADDR_BITS)
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val wen = Bool(INPUT)
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val taken = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val correct_pc = UInt(INPUT, VADDR_BITS)
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val correct_target = UInt(INPUT, VADDR_BITS)
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}
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val idxValid = Vec.fill(conf.entries){Reg(init=Bool(false))}
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val idxs = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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val pages = Vec.fill(conf.pages){Reg(UInt(width=VADDR_BITS-conf.matchBits))}
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val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))}
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private def page(addr: UInt) = addr >> conf.matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid.toBits
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}
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private def tagMatch(addr: UInt): UInt = tagMatch(addr, pageMatch(addr))
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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val idx = addr(conf.matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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idxValid.toBits & idxMatch & idxPageMatch
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}
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val hits = tagMatch(io.current_pc)
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val idxPageMatch = pageMatch(io.correct_pc)
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val tgtPageMatch = pageMatch(io.correct_target)
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val updates = tagMatch(io.correct_pc, idxPageMatch)
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val anyUpdates = updates.orR
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private var lfsr = LFSR16(io.wen)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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def randOrInvalid(valid: UInt) =
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Mux(!valid.andR, PriorityEncoderOH(~valid), rand(valid.getWidth))
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val idxRepl = randOrInvalid(idxValid.toBits)
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val idxWen = updates.toBits | idxRepl & ~anyUpdates.toSInt
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val useIdxPageMatch = idxPageMatch.orR
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val doIdxPageRepl = !useIdxPageMatch && io.taken
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val idxPageRepl = rand(conf.pages)
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val idxPageUpdate = Mux(useIdxPageMatch, idxPageMatch, idxPageRepl)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(io.correct_pc) === page(io.correct_target)
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val useTgtPageMatch = (tgtPageMatch & ~idxPageReplEn).orR
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val doTgtPageRepl = !useTgtPageMatch && io.taken && !samePage
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val tgtPageRepl = Mux(samePage, idxPageUpdate, idxPageUpdate(conf.pages-2,0) << 1 | idxPageUpdate(conf.pages-1))
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val tgtPageUpdate = Mux(useTgtPageMatch, tgtPageMatch, tgtPageRepl)
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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when (io.wen) {
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for (i <- 0 until conf.entries) {
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when (idxWen(i)) {
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idxValid(i) := io.taken
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when (io.taken) {
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idxs(i) := io.correct_pc
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idxPages(i) := OHToUInt(idxPageUpdate)
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tgts(i) := io.correct_target
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tgtPages(i) := OHToUInt(tgtPageUpdate)
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}
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}.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
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idxValid(i) := false
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}
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}
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require(conf.pages % 2 == 0)
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val idxWritesEven = (idxPageUpdate & Fill(conf.pages/2, UInt(1,2))).orR
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) = {
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for (i <- i until conf.pages by mod) {
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when (en && pageReplEn(i)) {
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pages(i) := data
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pageValid(i) := true
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}
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}
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}
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(io.correct_pc), page(io.correct_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(io.correct_target), page(io.correct_pc)))
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}
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when (io.invalidate) {
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idxValid.foreach(_ := false)
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pageValid.foreach(_ := false)
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}
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io.hit := hits.toBits.orR
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io.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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}
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