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rocket-chip/rocket/src/main/scala/btb.scala

217 lines
7.3 KiB
Scala
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package rocket
import Chisel._
import Util._
import Node._
import uncore._
case object Entries extends Field[Int]
case object NRAS extends Field[Int]
case object MatchBits extends Field[Int]
case object Pages0 extends Field[Int]
case object Pages extends Field[Int]
case object OpaqueBits extends Field[Int]
case object NBHT extends Field[Int]
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class RAS(nras: Int) {
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def push(addr: UInt): Unit = {
when (count < nras) { count := count + 1 }
val nextPos = Mux(Bool(isPow2(nras)) || pos > 0, pos+1, UInt(0))
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stack(nextPos) := addr
pos := nextPos
}
def peek: UInt = stack(pos)
def pop: Unit = when (!isEmpty) {
count := count - 1
pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
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}
def clear: Unit = count := UInt(0)
def isEmpty: Bool = count === UInt(0)
private val count = Reg(init=UInt(0,log2Up(nras+1)))
private val pos = Reg(init=UInt(0,log2Up(nras)))
private val stack = Vec.fill(nras){Reg(UInt())}
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}
class BHTResp extends Bundle {
val index = UInt(width = log2Up(params(NBHT)).max(1))
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val value = UInt(width = 2)
}
class BHT(nbht: Int) {
val nbhtbits = log2Up(nbht)
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def get(addr: UInt): BHTResp = {
val res = new BHTResp
res.index := addr(nbhtbits+1,2) ^ history
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res.value := table(res.index)
res
}
def update(d: BHTResp, taken: Bool): Unit = {
table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
history := Cat(taken, history(nbhtbits-1,1))
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}
private val table = Mem(UInt(width = 2), nbht)
val history = Reg(UInt(width = nbhtbits))
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}
class BTBUpdate extends Bundle {
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val prediction = Valid(new BTBResp)
val pc = UInt(width = params(VAddrBits))
val target = UInt(width = params(VAddrBits))
val returnAddr = UInt(width = params(VAddrBits))
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val taken = Bool()
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val isJump = Bool()
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val isCall = Bool()
val isReturn = Bool()
val incorrectTarget = Bool()
}
class BTBResp extends Bundle {
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val taken = Bool()
val target = UInt(width = params(VAddrBits))
val entry = UInt(width = params(OpaqueBits))
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val bht = new BHTResp
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}
// fully-associative branch target buffer
class BTB extends Module {
val io = new Bundle {
val req = UInt(INPUT, params(VAddrBits))
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val resp = Valid(new BTBResp)
val update = Valid(new BTBUpdate).flip
val invalidate = Bool(INPUT)
}
val idxValid = Reg(init=UInt(0, params(Entries)))
val idxs = Mem(UInt(width=params(MatchBits)), params(Entries))
val idxPages = Mem(UInt(width=log2Up(params(Pages))), params(Entries))
val tgts = Mem(UInt(width=params(MatchBits)), params(Entries))
val tgtPages = Mem(UInt(width=log2Up(params(Pages))), params(Entries))
val pages = Mem(UInt(width=params(VAddrBits)-params(MatchBits)), params(Pages))
val pageValid = Reg(init=UInt(0, params(Pages)))
val idxPagesOH = idxPages.map(UIntToOH(_)(params(Pages)-1,0))
val tgtPagesOH = tgtPages.map(UIntToOH(_)(params(Pages)-1,0))
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val useRAS = Reg(UInt(width = params(Entries)))
val isJump = Reg(UInt(width = params(Entries)))
private def page(addr: UInt) = addr >> params(MatchBits)
private def pageMatch(addr: UInt) = {
val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid
}
private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
val idx = addr(params(MatchBits)-1,0)
val idxMatch = idxs.map(_ === idx).toBits
val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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idxValid & idxMatch & idxPageMatch
}
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val update = Pipe(io.update)
val update_target = io.req
val pageHit = pageMatch(io.req)
val hits = tagMatch(io.req, pageHit)
val updatePageHit = pageMatch(update.bits.pc)
val updateHits = tagMatch(update.bits.pc, updatePageHit)
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private var lfsr = LFSR16(update.valid)
def rand(width: Int) = {
lfsr = lfsr(lfsr.getWidth-1,1)
Random.oneHot(width, lfsr)
}
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val updateHit = update.bits.prediction.valid
val updateValid = update.bits.incorrectTarget || updateHit && Bool(params(NBHT) > 0)
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val updateTarget = updateValid && update.bits.incorrectTarget
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
val idxPageRepl = UInt()
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(update.bits.pc) === page(update_target)
val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(params(Pages)-2,0) << 1 | idxPageUpdateOH(params(Pages)-1))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
val pageReplEn = idxPageReplEn | tgtPageReplEn
idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, params(Pages))._1)
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when (update.valid && !(updateValid && !updateTarget)) {
val nextRepl = Counter(!updateHit && updateValid, params(Entries))._1
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val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
idxValid := idxValid & ~Vec.tabulate(params(Entries))(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := updateValid
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when (updateTarget) {
assert(io.req === update.bits.target, "BTB request != I$ target")
idxs(waddr) := update.bits.pc
tgts(waddr) := update_target
idxPages(waddr) := idxPageUpdate
tgtPages(waddr) := tgtPageUpdate
useRAS(waddr) := update.bits.isReturn
isJump(waddr) := update.bits.isJump
}
require(params(Pages) % 2 == 0)
val idxWritesEven = (idxPageUpdateOH & Fill(params(Pages)/2, UInt(1,2))).orR
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
for (i <- i until params(Pages) by mod)
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when (en && pageReplEn(i)) { pages(i) := data }
writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(update.bits.pc), page(update_target)))
writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(update_target), page(update.bits.pc)))
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
}
when (io.invalidate) {
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idxValid := 0
pageValid := 0
}
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io.resp.valid := hits.orR
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io.resp.bits.taken := io.resp.valid
io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.entry := OHToUInt(hits)
if (params(NBHT) > 0) {
val bht = new BHT(params(NBHT))
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val res = bht.get(io.req)
when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
io.resp.bits.bht := res
}
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if (params(NRAS) > 0) {
val ras = new RAS(params(NRAS))
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val doPeek = Mux1H(hits, useRAS)
when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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when (io.update.valid) {
when (io.update.bits.isCall) {
ras.push(io.update.bits.returnAddr)
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when (doPeek) {
io.resp.bits.target := io.update.bits.returnAddr
}
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}.elsewhen (io.update.bits.isReturn && io.update.bits.prediction.valid) {
ras.pop
}
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}
when (io.invalidate) { ras.clear }
}
}