riscv/rocket-chip
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  • 1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges Wesley W. Terpstra 2016-09-14 18:18:59 -0700
  • 97809b183f refactor unittest framework Yunsup Lee 2016-09-14 18:10:21 -0700
  • d35060b881 [junctions] messed up the merge lulz Henry Cook 2016-09-14 17:55:16 -0700
  • 1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable Henry Cook 2016-09-14 17:50:17 -0700
  • e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. Henry Cook 2016-09-14 17:43:07 -0700
  • 3030718f72 bump chisel3 Henry Cook 2016-09-14 17:40:22 -0700
  • 08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO Henry Cook 2016-09-14 17:38:54 -0700
  • ae026edeb3 Merge pull request #293 from ucb-bar/async_clk_utils mwachs5 2016-09-14 16:59:27 -0700
  • 1308680f75 Add some async/clock utilities Megan Wachs 2016-09-14 16:30:59 -0700
  • 710f1ec020 Move BootROM from Coreplex to Periphery Yunsup Lee 2016-09-14 16:09:59 -0700
  • aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message Henry Cook 2016-09-14 14:56:50 -0700
  • d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? Henry Cook 2016-09-14 14:23:23 -0700
  • f7121a2a5b support for BSD sed (GNU sed still works) Scott Beamer 2016-09-14 11:34:23 -0700
  • cd12fd1cbb fix clang support for emulator-debug Scott Beamer 2016-09-14 11:36:47 -0700
  • 565444c40e Make UnitTestCoreplex cope with an external MMIO network Andrew Waterman 2016-09-14 12:18:55 -0700
  • 2572cd3f7c Add missing dependency Andrew Waterman 2016-09-14 11:50:28 -0700
  • 5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 Andrew Waterman 2016-09-14 11:47:10 -0700
  • c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs Andrew Waterman 2016-09-14 10:57:01 -0700
  • 5566bf1b13 Don't route PLIC interrupts through PRCI Andrew Waterman 2016-09-13 16:25:31 -0700
  • 38b13da2f4 Bump chisel and firrtl Andrew Waterman 2016-09-13 17:51:36 -0700
  • 47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) mwachs5 2016-09-14 00:17:26 -0700
  • bdb7b1de36 move tilelink-agnostic counters from uncore to util package Howard Mao 2016-09-13 20:29:42 -0700
  • 1882241493 move junctions utils into top-level utils package Howard Mao 2016-09-13 20:22:20 -0700
  • 7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. Henry Cook 2016-09-13 15:37:29 -0700
  • dfd6bfb454 Merge pull request #287 from ucb-bar/crossing-take-2 Wesley W. Terpstra 2016-09-13 19:13:21 -0700
  • d23ab7370d tilelink2: Unit Test for the RegisterCrossing Wesley W. Terpstra 2016-09-13 18:33:29 -0700
  • cc88bf1b08 junctions: give unit tests more time Wesley W. Terpstra 2016-09-13 17:41:35 -0700
  • acedd3688a tilelink2: unit test for the clock crossing Wesley W. Terpstra 2016-09-13 16:35:06 -0700
  • c8e6d47884 tilelink2: add a clock crossing adapter Wesley W. Terpstra 2016-09-13 16:04:46 -0700
  • 44501cdbf8 crossings: change defaults to sync=3 for safer settling time Wesley W. Terpstra 2016-09-13 15:49:08 -0700
  • 3348236320 junctions: remove obsolete Handshaker crossing Wesley W. Terpstra 2016-09-13 15:45:52 -0700
  • fe6a67dd0e tilelink2: add a RegisterCrossing primitive Wesley W. Terpstra 2016-09-13 15:26:59 -0700
  • d75f9d6a34 junctions: add an AsyncQueue Wesley W. Terpstra 2016-09-13 15:30:09 -0700
  • 8142406d2e junctions: refactor the Crossing type Wesley W. Terpstra 2016-09-13 15:34:56 -0700
  • ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain Wesley W. Terpstra 2016-09-07 13:55:22 -0700
  • 33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) Wesley W. Terpstra 2016-09-13 15:44:36 -0700
  • 28982ab569 Merge pull request #279 from ucb-bar/monitor Henry Cook 2016-09-13 14:04:23 -0700
  • 632b5896b9 Delete TestGraphs.scala Henry Cook 2016-09-13 13:29:48 -0700
  • e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. Henry Cook 2016-09-13 12:25:57 -0700
  • 05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor Henry Cook 2016-09-13 11:18:18 -0700
  • 61cbe6164d Add option to execute JAL from decode stage Andrew Waterman 2016-09-13 02:32:00 -0700
  • 606f19a17f tilelink2: RegisterRouter Unit Test Wesley W. Terpstra 2016-09-12 21:41:36 -0700
  • 7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op Wesley W. Terpstra 2016-09-12 19:06:35 -0700
  • 2979badf75 Update README.md roman3017 2016-09-11 18:26:56 -0700
  • 273d3a73f2 tilelink2: Unit Test passes! Wesley W. Terpstra 2016-09-12 18:39:50 -0700
  • a10d058e1a fix warnings in verilog source (#274) Colin Schmidt 2016-09-12 18:25:35 -0700
  • 9874bc553a tilelink2: Fragmenter supports Hints Wesley W. Terpstra 2016-09-12 17:31:59 -0700
  • 42955a0490 tilelink2: HintHandler optimize to nothing if unneeded Wesley W. Terpstra 2016-09-12 17:31:16 -0700
  • 94761f714d tilelink2 HintHandler: fill in correct sink in responses Wesley W. Terpstra 2016-09-12 17:26:40 -0700
  • ca5f98f138 tilelink2: Hints are not special Wesley W. Terpstra 2016-09-12 17:15:28 -0700
  • ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer Henry Cook 2016-09-12 16:55:29 -0700
  • 0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials Henry Cook 2016-09-12 15:31:26 -0700
  • c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData Henry Cook 2016-09-12 16:40:15 -0700
  • 82681179cb [tilelink2] Edges: add size to addr_lo. Henry Cook 2016-09-12 14:00:00 -0700
  • 88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) Andrew Waterman 2016-09-12 16:52:03 -0700
  • 266a2f24bd Disable Mul early out by default if XLen == 32 Andrew Waterman 2016-09-12 16:50:08 -0700
  • 96185e4b16 tighten an assert condition Andrew Waterman 2016-09-12 12:01:04 -0700
  • beb141a20b Allow M, A, D, C extensions to be disabled in misa register Andrew Waterman 2016-09-12 12:00:04 -0700
  • e66abb5e92 Merge pull request #276 from ucb-bar/nmemchannels-fix Andrew Waterman 2016-09-12 14:05:50 -0700
  • f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig Howard Mao 2016-09-12 12:40:10 -0700
  • 9d9f90646d allow configuration of simulation memory latency Howard Mao 2016-09-09 15:12:05 -0700
  • 49bba961cf Merge pull request #259 from ucb-bar/refactor-periphery Andrew Waterman 2016-09-12 12:18:00 -0700
  • a21b04a7c1 playground for making different DAGs to use as DUTs Henry Cook 2016-09-09 17:19:03 -0700
  • 0671d5d637 Initial version of fuzzer and simple ram fuzz test Henry Cook 2016-09-09 17:16:35 -0700
  • 7760459b76 tilelink2 RegisterRouter: add RegField test patterns Wesley W. Terpstra 2016-09-12 00:22:04 -0700
  • 85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible Wesley W. Terpstra 2016-09-11 15:44:56 -0700
  • 9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests Wesley W. Terpstra 2016-09-11 15:43:04 -0700
  • 26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug Wesley W. Terpstra 2016-09-10 01:22:12 -0700
  • 98a4facac7 tilelink2 RAMModel: clear Mems on power-up Wesley W. Terpstra 2016-09-10 00:24:57 -0700
  • 17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets Wesley W. Terpstra 2016-09-09 20:57:20 -0700
  • 488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull Wesley W. Terpstra 2016-09-09 20:56:48 -0700
  • d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code Wesley W. Terpstra 2016-09-09 20:55:56 -0700
  • 5604049927 tilelink2 Buffer: support an unlimited number of channels Wesley W. Terpstra 2016-09-09 11:08:39 -0700
  • d985cdfc66 Merge branch 'master' into refactor-periphery Yunsup Lee 2016-09-10 23:42:13 -0700
  • fea31c7061 let GlobalAddrMap and ConfigString overridable Yunsup Lee 2016-09-10 23:39:44 -0700
  • bb3f514e8d now able to add periphery devices through traits Yunsup Lee 2016-09-10 23:39:29 -0700
  • 395bc16da6 Merge pull request #271 from ucb-bar/black_box_regs_fix mwachs5 2016-09-10 14:14:12 -0700
  • 77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg Megan Wachs 2016-09-09 16:24:35 -0700
  • e6889ea711 Merge pull request #269 from ucb-bar/tweaks Andrew Waterman 2016-09-09 15:25:15 -0700
  • b695ab5292 Merge branch 'master' into tweaks Andrew Waterman 2016-09-09 15:04:21 -0700
  • 8273ca1ae7 Merge pull request #265 from ucb-bar/black_box_regs mwachs5 2016-09-09 13:54:04 -0700
  • 5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs Megan Wachs 2016-09-09 13:12:52 -0700
  • cf3c6fa277 add STOP_COND to emulator & match vsim PRINTF_COND Colin Schmidt 2016-09-09 10:57:10 -0700
  • 656aa78f7d Pipeline FMAs more deeply by default Andrew Waterman 2016-09-08 21:27:28 -0700
  • eaa4b04ee5 Check D$ store->load collisions more precisely Andrew Waterman 2016-09-07 18:29:41 -0700
  • c4593d2034 Merge pull request #266 from ucb-bar/multinode Henry Cook 2016-09-09 10:17:45 -0700
  • c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := Wesley W. Terpstra 2016-09-08 23:06:59 -0700
  • b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec Wesley W. Terpstra 2016-09-08 21:11:31 -0700
  • 176f385b1d Merge pull request #263 from ucb-bar/intbar Yunsup Lee 2016-09-08 21:33:25 -0700
  • 48ca478578 Merge branch 'master' into intbar Wesley W. Terpstra 2016-09-08 21:09:59 -0700
  • 808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) Wesley W. Terpstra 2016-09-08 21:09:40 -0700
  • fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 Megan Wachs 2016-09-08 20:01:03 -0700
  • c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices Megan Wachs 2016-09-08 13:49:29 -0700
  • cbf0670156 tilelink2 Legacy: it's only an error if it's valid Wesley W. Terpstra 2016-09-08 19:32:00 -0700
  • 1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters Wesley W. Terpstra 2016-09-08 18:51:43 -0700
  • 9015276958 Use sbt-launch.jar 0.13.12. (#262) Richard Xia 2016-09-08 17:26:04 -0700
  • 66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts Wesley W. Terpstra 2016-09-08 15:17:30 -0700
  • 23e896ed5d tilelink2 IntNodes: support interrupt graphs Wesley W. Terpstra 2016-09-08 11:30:35 -0700
  • d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages Wesley W. Terpstra 2016-09-08 14:41:08 -0700
  • 53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type Wesley W. Terpstra 2016-09-08 11:30:04 -0700