Merge remote-tracking branch 'origin/master' into black_box_regs
This commit is contained in:
Megan Wachs
commit
5f5989848c
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@ -39,10 +39,10 @@ class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
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object TLBuffer
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{
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// applied to the TL source node; connect (TLBuffer(x.node) -> y.node)
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def apply(x: TLBaseNode, entries: Int = 2, pipe: Boolean = false)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
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// applied to the TL source node; y.node := TLBuffer(x.node)
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def apply(x: TLBaseNode, entries: Int = 2, pipe: Boolean = false)(implicit sourceInfo: SourceInfo): TLBaseNode = {
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val buffer = LazyModule(new TLBuffer(entries, pipe))
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lazyModule.connect(x -> buffer.node)
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buffer.node := x
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buffer.node
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}
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}
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@ -16,14 +16,22 @@ trait ExampleModule extends HasRegMap
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{
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val params: ExampleParams
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val io: ExampleBundle
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val interrupts: Vec[Bool]
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val state = RegInit(UInt(0))
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io.gpio := state
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val pending = RegInit(UInt(0xf, width = 4))
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regmap(0 -> Seq(RegField(params.num, state)))
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io.gpio := state
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interrupts := pending.toBools
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regmap(
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0 -> Seq(
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RegField(params.num, state)),
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1 -> Seq(
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RegField.w1ToClear(4, pending, state)))
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}
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// Create a concrete TL2 version of the abstract Example slave
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class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address)(
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class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address, 4)(
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new TLRegBundle(p, _) with ExampleBundle)(
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new TLRegModule(p, _, _) with ExampleModule)
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@ -240,10 +240,10 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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object TLFragmenter
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{
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// applied to the TL source node; connect (TLFragmenter(x.node, 256, 4) -> y.node)
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def apply(x: TLBaseNode, minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
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// applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
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def apply(x: TLBaseNode, minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit sourceInfo: SourceInfo): TLBaseNode = {
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val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin))
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lazyModule.connect(x -> fragmenter.node)
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fragmenter.node := x
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fragmenter.node
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}
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}
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@ -90,10 +90,10 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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object TLHintHandler
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{
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// applied to the TL source node; connect (TLHintHandler(x.node) -> y.node)
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def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
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// applied to the TL source node; y.node := TLHintHandler(x.node)
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def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit sourceInfo: SourceInfo): TLBaseNode = {
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val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
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lazyModule.connect(x -> hints.node)
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hints.node := x
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hints.node
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}
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}
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@ -0,0 +1,94 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import scala.math.max
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import chisel3.internal.sourceinfo.SourceInfo
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// A potentially empty half-open range; [start, end)
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case class IntRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (start <= end)
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def size = end - start
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def overlaps(x: IntRange) = start < x.end && x.start < end
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def offset(x: Int) = IntRange(x+start, x+end)
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}
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object IntRange
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{
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implicit def apply(end: Int): IntRange = apply(0, end)
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}
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case class IntSourceParameters(device: String, range: IntRange)
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case class IntSinkPortParameters()
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case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
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{
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val num = sources.map(_.range.size).sum
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// The interrupts mapping must not overlap
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sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) }
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// The interrupts must perfectly cover the range
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require (sources.map(_.range.end).max == num)
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}
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
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object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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{
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def edgeO(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
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def edgeI(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
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def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = {
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if (eo.isEmpty) Vec(0, Vec(0, Bool())) else
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Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
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}
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def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
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require (!ei.isEmpty)
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Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip
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}
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def connect(bo: Vec[Bool], eo: IntEdge, bi: Vec[Bool], ei: IntEdge)(implicit sourceInfo: SourceInfo): Unit = {
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require (eo == ei)
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// Cannot use bulk connect, because the widths could differ
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(bo zip bi) foreach { case (o, i) => i := o }
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}
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}
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case class IntIdentityNode() extends IdentityNode(IntImp)
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case class IntOutputNode() extends OutputNode(IntImp)
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case class IntInputNode() extends InputNode(IntImp)
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case class IntSourceNode(device: String, num: Int) extends SourceNode(IntImp)(
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IntSourcePortParameters(Seq(IntSourceParameters(device, num))),
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(if (num == 0) 0 else 1) to 1)
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case class IntSinkNode() extends SinkNode(IntImp)(IntSinkPortParameters())
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case class IntAdapterNode(
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sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
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sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters,
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numSourcePorts: Range.Inclusive = 1 to 1,
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numSinkPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
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class IntXbar extends LazyModule
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{
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val intnode = IntAdapterNode(
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numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink?
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numSinkPorts = 1 to 128,
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sinkFn = { _ => IntSinkPortParameters() },
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sourceFn = { seq =>
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IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten)
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})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = intnode.bundleIn
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val out = intnode.bundleOut
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}
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val cat = (intnode.edgesIn zip io.in).map{ case (e, i) => i.take(e.source.num) }.flatten
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io.out.foreach { _ := cat }
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}
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}
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@ -3,12 +3,13 @@
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo._
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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abstract class LazyModule
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{
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protected[tilelink2] var bindings = List[() => Unit]()
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protected[tilelink2] var children = List[LazyModule]()
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protected[tilelink2] var nodes = List[RootNode]()
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protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo
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protected[tilelink2] val parent = LazyModule.stack.headOption
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@ -16,14 +17,14 @@ abstract class LazyModule
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parent.foreach(p => p.children = this :: p.children)
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// Use as: connect(source -> sink, source2 -> sink2, ...)
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def connect[PO, PI, EO, EI, B <: Bundle](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
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edges.foreach { case (source, sink) =>
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bindings = (source edge sink) :: bindings
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}
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def connect[PO, PI, EO, EI, B <: Data](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
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edges.foreach { case (source, sink) => sink := source }
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}
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def name = getClass.getName.split('.').last
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def line = sourceLine(info)
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def module: LazyModuleImp
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implicit val lazyModule = this
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protected[tilelink2] def instantiate() = {
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children.reverse.foreach { c =>
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@ -43,7 +44,8 @@ object LazyModule
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// Make sure the user put LazyModule around modules in the correct order
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// If this require fails, probably some grandchild was missing a LazyModule
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// ... or you applied LazyModule twice
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require (!stack.isEmpty && (stack.head eq bc))
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require (!stack.isEmpty, s"LazyModule() applied to ${bc.name} twice ${sourceLine(sourceInfo)}")
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require (stack.head eq bc, s"LazyModule() applied to ${bc.name} before ${stack.head.name} ${sourceLine(sourceInfo)}")
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stack = stack.tail
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bc.info = sourceInfo
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bc
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@ -53,8 +55,8 @@ object LazyModule
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abstract class LazyModuleImp(outer: LazyModule) extends Module
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{
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// .module had better not be accessed while LazyModules are still being built!
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require (LazyModule.stack.isEmpty)
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require (LazyModule.stack.isEmpty, s"${outer.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}")
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override def desiredName = outer.getClass.getName.split('.').last
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override def desiredName = outer.name
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outer.instantiate()
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}
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@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.SourceInfo
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// PO = PortOutputParameters
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// EI = EdgeInput
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// EO = EdgeOutput
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abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
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abstract class NodeImp[PO, PI, EO, EI, B <: Data]
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{
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def edgeO(po: PO, pi: PI): EO
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def edgeI(po: PO, pi: PI): EI
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@ -19,36 +19,56 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
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def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit
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}
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class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
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private val oFn: Option[Seq[PO] => PO],
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private val iFn: Option[Seq[PI] => PI],
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class RootNode
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{
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// You cannot create a Node outside a LazyModule!
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require (!LazyModule.stack.isEmpty)
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val lazyModule = LazyModule.stack.head
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lazyModule.nodes = this :: lazyModule.nodes
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}
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class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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private val oFn: (Int, Seq[PO]) => Seq[PO],
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private val iFn: (Int, Seq[PI]) => Seq[PI],
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private val numPO: Range.Inclusive,
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private val numPI: Range.Inclusive)
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private val numPI: Range.Inclusive) extends RootNode
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{
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// At least 0 ports must be supported
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require (!numPO.isEmpty)
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require (!numPI.isEmpty)
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require (numPO.start >= 0)
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require (numPI.start >= 0)
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def name = lazyModule.name + "." + getClass.getName.split('.').last
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
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val noOs = numPO.size == 1 && numPO.contains(0)
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (noOs || oFn.isDefined)
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require (noIs || iFn.isDefined)
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private val accPO = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accPI = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accPO = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
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private val accPI = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
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private var oRealized = false
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private var iRealized = false
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|
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private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() }
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private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() }
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private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
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private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
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private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
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protected def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
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|
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lazy val edgesOut = oPorts.map { n => imp.edgeO(oParams.get, n.iParams.get) }
|
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lazy val edgesIn = iPorts.map { n => imp.edgeI(n.oParams.get, iParams.get) }
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private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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|
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private lazy val oParams : Seq[PO] = {
|
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val o = oFn(oPorts.size, iPorts.map{ case (i, n) => n.oParams(i) })
|
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reqE(oPorts.size, o.size)
|
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o
|
||||
}
|
||||
private lazy val iParams : Seq[PI] = {
|
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val i = iFn(iPorts.size, oPorts.map{ case (o, n) => n.iParams(o) })
|
||||
reqE(i.size, iPorts.size)
|
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i
|
||||
}
|
||||
|
||||
lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => imp.edgeO(o, n.iParams(i)) }
|
||||
lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => imp.edgeI(n.oParams(o), i) }
|
||||
|
||||
lazy val bundleOut = imp.bundleO(edgesOut)
|
||||
lazy val bundleIn = imp.bundleI(edgesIn)
|
||||
|
|
@ -56,53 +76,55 @@ class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
|
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def connectOut = bundleOut
|
||||
def connectIn = bundleIn
|
||||
|
||||
// source.edge(sink)
|
||||
protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
|
||||
require (!noOs)
|
||||
require (!oRealized)
|
||||
require (!x.noIs)
|
||||
require (!x.iRealized)
|
||||
protected[tilelink2] def := (y: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
|
||||
val x = this // x := y
|
||||
val info = sourceLine(sourceInfo, " at ", "")
|
||||
require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
|
||||
require (!y.noOs, s"${y.name}${y.lazyModule.line} was incorrectly connected as a source" + info)
|
||||
require (!y.oRealized, s"${y.name}${y.lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
|
||||
require (!x.noIs, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink" + info)
|
||||
require (!x.iRealized, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
|
||||
val i = x.accPI.size
|
||||
val o = accPO.size
|
||||
accPO += x
|
||||
x.accPI += this
|
||||
() => {
|
||||
imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
|
||||
}
|
||||
val o = y.accPO.size
|
||||
y.accPO += ((i, x))
|
||||
x.accPI += ((o, y))
|
||||
LazyModule.stack.head.bindings = (() => {
|
||||
imp.connect(y.connectOut(o), y.edgesOut(o), x.connectIn(i), x.edgesIn(i))
|
||||
}) :: LazyModule.stack.head.bindings
|
||||
}
|
||||
}
|
||||
|
||||
class IdentityNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
|
||||
extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
|
||||
class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
|
||||
extends BaseNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
|
||||
|
||||
class OutputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
|
||||
class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
|
||||
{
|
||||
override def connectOut = bundleOut
|
||||
override def connectIn = bundleOut
|
||||
}
|
||||
|
||||
class InputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
|
||||
class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
|
||||
{
|
||||
override def connectOut = bundleIn
|
||||
override def connectIn = bundleIn
|
||||
}
|
||||
|
||||
class SourceNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
|
||||
extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0)
|
||||
class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
|
||||
extends BaseNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
|
||||
{
|
||||
require (num.end >= 1)
|
||||
require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
|
||||
}
|
||||
|
||||
class SinkNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
|
||||
extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num)
|
||||
class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
|
||||
extends BaseNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
|
||||
{
|
||||
require (num.end >= 1)
|
||||
require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
|
||||
}
|
||||
|
||||
class InteriorNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
|
||||
class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
|
||||
(oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
|
||||
extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI)
|
||||
extends BaseNode(imp)({case (n,s) => Seq.fill(n)(oFn(s))}, {case (n,s) => Seq.fill(n)(iFn(s))}, numPO, numPI)
|
||||
{
|
||||
require (numPO.end >= 1)
|
||||
require (numPI.end >= 1)
|
||||
require (numPO.end >= 1, s"${name} is an adapter which does not accept outputs${lazyModule.line}")
|
||||
require (numPI.end >= 1, s"${name} is an adapter which does not accept inputs${lazyModule.line}")
|
||||
}
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ object RegField
|
|||
trait HasRegMap
|
||||
{
|
||||
def regmap(mapping: RegField.Map*): Unit
|
||||
val interrupts: Vec[Bool]
|
||||
}
|
||||
|
||||
// See GPIO.scala for an example of how to use regmap
|
||||
|
|
|
|||
|
|
@ -75,29 +75,39 @@ object TLRegisterNode
|
|||
// register mapped device from a totally abstract register mapped device.
|
||||
// See GPIO.scala in this directory for an example
|
||||
|
||||
abstract class TLRegisterRouterBase(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends LazyModule
|
||||
abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int) extends LazyModule
|
||||
{
|
||||
val node = TLRegisterNode(address, concurrency, beatBytes)
|
||||
val intnode = IntSourceNode(name + s" @ ${address.base}", interrupts)
|
||||
}
|
||||
|
||||
class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
|
||||
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])
|
||||
|
||||
class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
|
||||
class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
|
||||
{
|
||||
val interrupts = arg.interrupts
|
||||
val in = arg.in
|
||||
}
|
||||
|
||||
class TLRegBundle[P](val params: P, arg: TLRegBundleArg) extends TLRegBundleBase(arg)
|
||||
|
||||
class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
|
||||
extends LazyModuleImp(router) with HasRegMap
|
||||
{
|
||||
val io = bundleBuilder
|
||||
val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
|
||||
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
|
||||
}
|
||||
|
||||
class TLRegisterRouter[B <: Bundle, M <: LazyModuleImp]
|
||||
(base: BigInt, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
|
||||
(bundleBuilder: Vec[TLBundle] => B)
|
||||
class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp]
|
||||
(base: BigInt, interrupts: Int = 0, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
|
||||
(bundleBuilder: TLRegBundleArg => B)
|
||||
(moduleBuilder: (=> B, TLRegisterRouterBase) => M)
|
||||
extends TLRegisterRouterBase(AddressSet(base, size-1), concurrency, beatBytes)
|
||||
extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes)
|
||||
{
|
||||
require (size % 4096 == 0) // devices should be 4K aligned
|
||||
require (isPow2(size))
|
||||
require (size >= 4096)
|
||||
|
||||
lazy val module = moduleBuilder(bundleBuilder(node.bundleIn), this)
|
||||
lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -171,10 +171,10 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
|
|||
|
||||
object TLWidthWidget
|
||||
{
|
||||
// applied to the TL source node; connect (WidthWidget(x.node, 16) -> y.node)
|
||||
def apply(x: TLBaseNode, innerBeatBytes: Int)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
|
||||
// applied to the TL source node; y.node := WidthWidget(x.node, 16)
|
||||
def apply(x: TLBaseNode, innerBeatBytes: Int)(implicit sourceInfo: SourceInfo): TLBaseNode = {
|
||||
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
|
||||
lazyModule.connect(x -> widget.node)
|
||||
widget.node := x
|
||||
widget.node
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,18 @@
|
|||
package uncore
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
|
||||
|
||||
package object tilelink2
|
||||
{
|
||||
type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
|
||||
type IntBaseNode = BaseNode[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
|
||||
def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
|
||||
def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
|
||||
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
|
||||
|
||||
def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
|
||||
case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
|
||||
case _ => ""
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue