Merge pull request #293 from ucb-bar/async_clk_utils
Add some async/clock utilities
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commit
ae026edeb3
@ -50,3 +50,44 @@ object AsyncDecoupledFrom
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AsyncDecoupledCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
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}
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}
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/** Because Chisel/FIRRTL does not allow us
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* to directly assign clocks from Signals,
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* we need this black box module.
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* This may even be useful because some back-end
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* flows like to have this sort of transition
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* flagged with a special cell or module anyway.
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*/
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class SignalToClock extends BlackBox {
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val io = new Bundle {
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val signal_in = Bool(INPUT)
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val clock_out = Clock(OUTPUT)
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}
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// io.clock_out := io.signal_in
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}
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object SignalToClock {
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def apply(signal: Bool): Clock = {
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val s2c = Module(new SignalToClock)
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s2c.io.signal_in := signal
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s2c.io.clock_out
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}
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}
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class ClockToSignal extends BlackBox {
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val io = new Bundle {
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val clock_in = Clock(INPUT)
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val signal_out = Bool(OUTPUT)
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}
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}
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object ClockToSignal {
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def apply(clk: Clock): Bool = {
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val c2s = Module(new ClockToSignal)
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c2s.io.clock_in := clk
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c2s.io.signal_out
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}
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}
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@ -4,6 +4,7 @@ package uncore.tilelink2
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import Chisel._
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import junctions._
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import uncore.util.{AsyncResetRegVec}
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// A very simple flow control state machine, run in the specified clock domain
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class BusyRegisterCrossing(clock: Clock, reset: Bool)
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@ -130,3 +131,56 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
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crossing.io.deq.ready := io.master_port.request.valid && !reg.io.busy
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crossing.io.enq.valid := Bool(true)
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}
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/** Wrapper to create an
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* asynchronously reset
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* slave register which
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* can be both read
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* and written using
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* crossing FIFOs.
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*/
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object AsyncRWSlaveRegField {
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def apply(slave_clock: Clock,
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slave_reset: Bool,
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width: Int,
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init: Int,
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master_allow: Bool = Bool(true),
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slave_allow: Bool = Bool(true)
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): (UInt, RegField) = {
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val async_slave_reg = Module(new AsyncResetRegVec(width, init))
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async_slave_reg.reset := slave_reset
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async_slave_reg.clock := slave_clock
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val wr_crossing = Module (new RegisterWriteCrossing(UInt(width = width)))
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val scope = Module (new AsyncScope())
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wr_crossing.io.master_clock := scope.clock
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wr_crossing.io.master_reset := scope.reset
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wr_crossing.io.master_allow := master_allow
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wr_crossing.io.slave_clock := slave_clock
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wr_crossing.io.slave_reset := slave_reset
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wr_crossing.io.slave_allow := slave_allow
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async_slave_reg.io.en := wr_crossing.io.slave_valid
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async_slave_reg.io.d := wr_crossing.io.slave_register
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val rd_crossing = Module (new RegisterReadCrossing(UInt(width = width )))
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rd_crossing.io.master_clock := scope.clock
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rd_crossing.io.master_reset := scope.reset
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rd_crossing.io.master_allow := master_allow
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rd_crossing.io.slave_clock := slave_clock
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rd_crossing.io.slave_reset := slave_reset
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rd_crossing.io.slave_allow := slave_allow
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rd_crossing.io.slave_register := async_slave_reg.io.q
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(async_slave_reg.io.q, RegField(width, rd_crossing.io.master_port, wr_crossing.io.master_port))
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}
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}
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@ -9,6 +9,9 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
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$(base_dir)/vsrc/AsyncMailbox.v \
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$(base_dir)/vsrc/AsyncResetReg.v \
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$(base_dir)/vsrc/ClockDivider.v \
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$(base_dir)/vsrc/ClockToSignal.v \
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$(base_dir)/vsrc/SignalToClock.v \
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).$(CONFIG).v \
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19
vsrc/ClockToSignal.v
Normal file
19
vsrc/ClockToSignal.v
Normal file
@ -0,0 +1,19 @@
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/* This blackbox is needed by
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* Chisel in order to do type conversion.
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* It may be useful for some synthesis flows
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* as well which require special
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* flagging on conversion from data to clock.
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*/
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module ClockToSignal(
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output signal_out,
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input clock_in
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);
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assign signal_out = clock_in;
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endmodule // ClockToSignal
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18
vsrc/SignalToClock.v
Normal file
18
vsrc/SignalToClock.v
Normal file
@ -0,0 +1,18 @@
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/* This blackbox is needed by
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* Chisel in order to do type conversion.
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* It may be useful for some synthesis flows
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* as well which require special
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* flagging on conversion from data to clock.
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*/
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module SignalToClock (
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output clock_out,
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input signal_in
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);
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assign clock_out = signal_in;
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endmodule // SignalToClock
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