add STOP_COND to emulator & match vsim PRINTF_COND
This commit is contained in:
parent
656aa78f7d
commit
cf3c6fa277
@ -15,6 +15,7 @@
|
||||
extern dtm_t* dtm;
|
||||
static uint64_t trace_count = 0;
|
||||
bool verbose;
|
||||
bool done_reset;
|
||||
|
||||
void handle_sigterm(int sig)
|
||||
{
|
||||
@ -89,6 +90,7 @@ int main(int argc, char** argv)
|
||||
tile->eval();
|
||||
tile->reset = 0;
|
||||
}
|
||||
done_reset = true;
|
||||
|
||||
while (!dtm->done() && !tile->io_success && trace_count < max_cycles) {
|
||||
tile->clk = 0;
|
||||
|
@ -6,6 +6,7 @@
|
||||
#include <stdio.h>
|
||||
|
||||
extern bool verbose;
|
||||
extern bool done_reset;
|
||||
|
||||
class VerilatedVcdFILE : public VerilatedVcdFile {
|
||||
public:
|
||||
|
@ -49,7 +49,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
|
||||
|
||||
# Run Verilator to produce a fast binary to emulate this circuit.
|
||||
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
|
||||
VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
|
||||
VERILATOR_FLAGS := --top-module $(MODEL) \
|
||||
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
|
||||
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
|
||||
-Wno-STMTDLY --x-assign unique \
|
||||
-I$(base_dir)/vsrc \
|
||||
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
|
||||
|
Loading…
Reference in New Issue
Block a user