Merge branch 'master' into refactor-periphery

csrc/emulator.cc

@@ -15,6 +15,7 @@
 extern dtm_t* dtm;
 static uint64_t trace_count = 0;
 bool verbose;
+bool done_reset;
 
 void handle_sigterm(int sig)
 {
@@ -89,6 +90,7 @@ int main(int argc, char** argv)
     tile->eval();
     tile->reset = 0;
   }
+  done_reset = true;
 
   while (!dtm->done() && !tile->io_success && trace_count < max_cycles) {
     tile->clk = 0;

csrc/verilator.h

@@ -6,6 +6,7 @@
 #include <stdio.h>
 
 extern bool verbose;
+extern bool done_reset;
 
 class VerilatedVcdFILE : public VerilatedVcdFile {
  public:

emulator/Makefrag-verilator

@@ -49,7 +49,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
 
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
-VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
+VERILATOR_FLAGS := --top-module $(MODEL) \
+  +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+  +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
 	-Wno-STMTDLY --x-assign unique \
   -I$(base_dir)/vsrc \
   -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"

src/main/scala/rocket/dcache.scala

@@ -173,9 +173,9 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   when (s2_valid && (!s2_valid_hit || s2_update_meta)) { s1_nack := true }
 
   // exceptions
-  val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).misaligned
-  io.cpu.xcpt.ma.ld := s1_read && misaligned
-  io.cpu.xcpt.ma.st := s1_write && misaligned
+  val s1_storegen = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes)
+  io.cpu.xcpt.ma.ld := s1_read && s1_storegen.misaligned
+  io.cpu.xcpt.ma.st := s1_write && s1_storegen.misaligned
   io.cpu.xcpt.pf.ld := s1_read && tlb.io.resp.xcpt_ld
   io.cpu.xcpt.pf.st := s1_write && tlb.io.resp.xcpt_st
 
@@ -232,8 +232,8 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   // store->load RAW hazard detection
   val s1_idx = s1_req.addr(idxMSB, wordOffBits)
   val s1_raw_hazard = s1_read &&
-    ((pstore1_valid && pstore1_addr(idxMSB, wordOffBits) === s1_idx) ||
-     (pstore2_valid && pstore2_addr(idxMSB, wordOffBits) === s1_idx))
+    ((pstore1_valid && pstore1_addr(idxMSB, wordOffBits) === s1_idx && (pstore1_storegen.mask & s1_storegen.mask).orR) ||
+     (pstore2_valid && pstore2_addr(idxMSB, wordOffBits) === s1_idx && (pstore2_storegen_mask & s1_storegen.mask).orR))
   when (s1_valid && s1_raw_hazard) { s1_nack := true }
 
   metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_update_meta) || (s2_victimize && !s2_victim_dirty)

src/main/scala/rocket/fpu.scala

@@ -12,8 +12,8 @@ import cde.{Parameters, Field}
 
 case class FPUConfig(
   divSqrt: Boolean = true,
-  sfmaLatency: Int = 2,
-  dfmaLatency: Int = 3
+  sfmaLatency: Int = 3,
+  dfmaLatency: Int = 4
 )
 
 object FPConstants

src/main/scala/uncore/tilelink2/Buffer.scala

@@ -39,10 +39,10 @@ class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
 
 object TLBuffer
 {
-  // applied to the TL source node; connect (TLBuffer(x.node) -> y.node)
-  def apply(x: TLBaseNode, entries: Int = 2, pipe: Boolean = false)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
+  // applied to the TL source node; y.node := TLBuffer(x.node)
+  def apply(x: TLBaseNode, entries: Int = 2, pipe: Boolean = false)(implicit sourceInfo: SourceInfo): TLBaseNode = {
     val buffer = LazyModule(new TLBuffer(entries, pipe))
-    lazyModule.connect(x -> buffer.node)
+    buffer.node := x
     buffer.node
   }
 }

src/main/scala/uncore/tilelink2/Bundles.scala

@@ -100,7 +100,7 @@ object TLAtomics
   def isLogical(x: UInt) = x <= SWAP
 }
 
-sealed trait TLChannel
+sealed trait TLChannel extends TLBundleBase
 sealed trait TLDataChannel extends TLChannel
 sealed trait TLAddrChannel extends TLDataChannel
 
@@ -165,7 +165,7 @@ final class TLBundleD(params: TLBundleParameters)
 final class TLBundleE(params: TLBundleParameters)
   extends TLBundleBase(params) with TLChannel
 {
-  val sink = UInt(width = params.sourceBits) // to
+  val sink = UInt(width = params.sinkBits) // to
 }
 
 class TLBundle(params: TLBundleParameters) extends TLBundleBase(params)

src/main/scala/uncore/tilelink2/Edges.scala

@@ -27,7 +27,7 @@ class TLEdge(
   // This gets used everywhere, so make the smallest circuit possible ...
   def mask(addr_lo: UInt, lgSize: UInt): UInt = {
     val lgBytes = log2Ceil(manager.beatBytes)
-    val sizeOH = UIntToOH(lgSize, lgBytes)
+    val sizeOH = UIntToOH(lgSize, log2Up(manager.beatBytes))
     def helper(i: Int): Seq[(Bool, Bool)] = {
       if (i == 0) {
         Seq((lgSize >= UInt(lgBytes), Bool(true)))

src/main/scala/uncore/tilelink2/Example.scala

@@ -0,0 +1,37 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+
+case class ExampleParams(num: Int, address: BigInt)
+
+trait ExampleBundle
+{
+  val params: ExampleParams
+  val gpio = UInt(width = params.num)
+}
+
+trait ExampleModule extends HasRegMap
+{
+  val params: ExampleParams
+  val io: ExampleBundle
+  val interrupts: Vec[Bool]
+
+  val state = RegInit(UInt(0))
+  val pending = RegInit(UInt(0xf, width = 4))
+
+  io.gpio := state
+  interrupts := pending.toBools
+
+  regmap(
+    0 -> Seq(
+      RegField(params.num, state)),
+    1 -> Seq(
+      RegField.w1ToClear(4, pending, state)))
+}
+
+// Create a concrete TL2 version of the abstract Example slave
+class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address, 4)(
+  new TLRegBundle(p, _)    with ExampleBundle)(
+  new TLRegModule(p, _, _) with ExampleModule)

src/main/scala/uncore/tilelink2/Fragmenter.scala

@@ -240,10 +240,10 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
 
 object TLFragmenter
 {
-  // applied to the TL source node; connect (TLFragmenter(x.node, 256, 4) -> y.node)
-  def apply(x: TLBaseNode, minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
+  // applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
+  def apply(x: TLBaseNode, minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit sourceInfo: SourceInfo): TLBaseNode = {
     val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin))
-    lazyModule.connect(x -> fragmenter.node)
+    fragmenter.node := x
     fragmenter.node
   }
 }

src/main/scala/uncore/tilelink2/GPIO.scala

@@ -1,29 +0,0 @@
-// See LICENSE for license details.
-
-package uncore.tilelink2
-
-import Chisel._
-
-case class GPIOParams(num: Int, address: BigInt)
-
-trait GPIOBundle
-{
-  val params: GPIOParams
-  val gpio = UInt(width = params.num)
-}
-
-trait GPIOModule extends HasRegMap
-{
-  val params: GPIOParams
-  val io: GPIOBundle
-
-  val state = RegInit(UInt(0))
-  io.gpio := state
-
-  regmap(0 -> Seq(RegField(params.num, state)))
-}
-
-// Create a concrete TL2 version of the abstract GPIO slave
-class TLGPIO(p: GPIOParams) extends TLRegisterRouter(p.address)(
-  new TLRegBundle(p, _)    with GPIOBundle)(
-  new TLRegModule(p, _, _) with GPIOModule)

src/main/scala/uncore/tilelink2/HintHandler.scala

@@ -90,10 +90,10 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
 
 object TLHintHandler
 {
-  // applied to the TL source node; connect (TLHintHandler(x.node) -> y.node)
-  def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
+  // applied to the TL source node; y.node := TLHintHandler(x.node)
+  def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit sourceInfo: SourceInfo): TLBaseNode = {
     val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
-    lazyModule.connect(x -> hints.node)
+    hints.node := x
     hints.node
   }
 }

src/main/scala/uncore/tilelink2/IntNodes.scala

@@ -0,0 +1,94 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+import scala.collection.mutable.ListBuffer
+import scala.math.max
+import chisel3.internal.sourceinfo.SourceInfo
+
+// A potentially empty half-open range; [start, end)
+case class IntRange(start: Int, end: Int)
+{
+  require (start >= 0)
+  require (start <= end)
+  def size = end - start
+  def overlaps(x: IntRange) = start < x.end && x.start < end
+  def offset(x: Int) = IntRange(x+start, x+end)
+}
+object IntRange
+{
+  implicit def apply(end: Int): IntRange = apply(0, end)
+}
+
+case class IntSourceParameters(device: String, range: IntRange)
+
+case class IntSinkPortParameters()
+case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
+{
+  val num = sources.map(_.range.size).sum
+  // The interrupts mapping must not overlap
+  sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) }
+  // The interrupts must perfectly cover the range
+  require (sources.map(_.range.end).max == num)
+}
+case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
+
+object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
+{
+  def edgeO(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
+  def edgeI(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
+  def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = {
+    if (eo.isEmpty) Vec(0, Vec(0, Bool())) else
+    Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
+  }
+  def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
+    require (!ei.isEmpty)
+    Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip
+  }
+
+  def connect(bo: Vec[Bool], eo: IntEdge, bi: Vec[Bool], ei: IntEdge)(implicit sourceInfo: SourceInfo): Unit = {
+    require (eo == ei)
+    // Cannot use bulk connect, because the widths could differ
+    (bo zip bi) foreach { case (o, i) => i := o }
+  }
+}
+
+case class IntIdentityNode() extends IdentityNode(IntImp)
+case class IntOutputNode() extends OutputNode(IntImp)
+case class IntInputNode() extends InputNode(IntImp)
+
+case class IntSourceNode(device: String, num: Int) extends SourceNode(IntImp)(
+  IntSourcePortParameters(Seq(IntSourceParameters(device, num))),
+  (if (num == 0) 0 else 1) to 1)
+case class IntSinkNode() extends SinkNode(IntImp)(IntSinkPortParameters())
+
+case class IntAdapterNode(
+  sourceFn:       Seq[IntSourcePortParameters] => IntSourcePortParameters,
+  sinkFn:         Seq[IntSinkPortParameters]   => IntSinkPortParameters,
+  numSourcePorts: Range.Inclusive = 1 to 1,
+  numSinkPorts:   Range.Inclusive = 1 to 1)
+  extends InteriorNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
+
+class IntXbar extends LazyModule
+{
+  val intnode = IntAdapterNode(
+    numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink?
+    numSinkPorts   = 1 to 128,
+    sinkFn         = { _ => IntSinkPortParameters() },
+    sourceFn       = { seq =>
+      IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
+        case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
+      }.flatten)
+    })
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in  = intnode.bundleIn
+      val out = intnode.bundleOut
+    }
+
+    val cat = (intnode.edgesIn zip io.in).map{ case (e, i) => i.take(e.source.num) }.flatten
+    io.out.foreach { _ := cat }
+  }
+}

src/main/scala/uncore/tilelink2/LazyModule.scala

@@ -3,12 +3,13 @@
 package uncore.tilelink2
 
 import Chisel._
-import chisel3.internal.sourceinfo._
+import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
 
 abstract class LazyModule
 {
   protected[tilelink2] var bindings = List[() => Unit]()
   protected[tilelink2] var children = List[LazyModule]()
+  protected[tilelink2] var nodes = List[RootNode]()
   protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo
   protected[tilelink2] val parent = LazyModule.stack.headOption
 
@@ -16,14 +17,14 @@ abstract class LazyModule
   parent.foreach(p => p.children = this :: p.children)
 
   // Use as: connect(source -> sink, source2 -> sink2, ...)
-  def connect[PO, PI, EO, EI, B <: Bundle](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
-    edges.foreach { case (source, sink) =>
-      bindings = (source edge sink) :: bindings
-    }
+  def connect[PO, PI, EO, EI, B <: Data](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
+    edges.foreach { case (source, sink) => sink := source }
   }
 
+  def name = getClass.getName.split('.').last
+  def line = sourceLine(info)
+
   def module: LazyModuleImp
-  implicit val lazyModule = this
 
   protected[tilelink2] def instantiate() = {
     children.reverse.foreach { c => 
@@ -43,7 +44,8 @@ object LazyModule
     // Make sure the user put LazyModule around modules in the correct order
     // If this require fails, probably some grandchild was missing a LazyModule
     // ... or you applied LazyModule twice
-    require (!stack.isEmpty && (stack.head eq bc))
+    require (!stack.isEmpty, s"LazyModule() applied to ${bc.name} twice ${sourceLine(sourceInfo)}")
+    require (stack.head eq bc, s"LazyModule() applied to ${bc.name} before ${stack.head.name} ${sourceLine(sourceInfo)}")
     stack = stack.tail
     bc.info = sourceInfo
     bc
@@ -53,8 +55,8 @@ object LazyModule
 abstract class LazyModuleImp(outer: LazyModule) extends Module
 {
   // .module had better not be accessed while LazyModules are still being built!
-  require (LazyModule.stack.isEmpty)
+  require (LazyModule.stack.isEmpty, s"${outer.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}")
 
-  override def desiredName = outer.getClass.getName.split('.').last
+  override def desiredName = outer.name
   outer.instantiate()
 }

src/main/scala/uncore/tilelink2/Legacy.scala

@@ -107,7 +107,7 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
     out.a.bits.addr_hi := ~(~address | addressMask) >> log2Ceil(tlDataBytes)
 
     // TL legacy does not support bus errors
-    assert (!out.d.bits.error)
+    assert (!out.d.valid || !out.d.bits.error)
 
     // Recreate the beat address counter
     val beatCounter = RegInit(UInt(0, width = tlBeatAddrBits))

src/main/scala/uncore/tilelink2/Narrower.scala

@@ -1,138 +0,0 @@
-// See LICENSE for license details.
-
-package uncore.tilelink2
-
-import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
-import scala.math.{min,max}
-
-// innBeatBytes => the bus width after the adapter
-class TLNarrower(innerBeatBytes: Int) extends LazyModule
-{
-  val node = TLAdapterNode(
-    clientFn  = { case Seq(c) => c },
-    managerFn = { case Seq(m) => m.copy(beatBytes = innerBeatBytes) })
-
-  lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
-      val in  = node.bundleIn
-      val out = node.bundleOut
-    }
-
-    val edgeOut = node.edgesOut(0)
-    val edgeIn  = node.edgesIn(0)
-    val outerBeatBytes = edgeOut.manager.beatBytes
-    require (outerBeatBytes < innerBeatBytes)
-
-    val ratio = innerBeatBytes / outerBeatBytes
-    val bce = edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe
-
-    def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
-
-    def split(edge: TLEdge, in: TLDataChannel, fire: Bool): (Bool, UInt, UInt) = {
-      val dataSlices = Vec.tabulate (ratio) { i => edge.data(in)((i+1)*outerBeatBytes*8-1, i*outerBeatBytes*8) }
-      val maskSlices = Vec.tabulate (ratio) { i => edge.mask(in)((i+1)*outerBeatBytes  -1, i*outerBeatBytes)   }
-      val filter = Reg(UInt(width = ratio), init = SInt(-1, width = ratio).asUInt)
-      val mask = maskSlices.map(_.orR)
-      val hasData = edge.hasData(in)
-
-      // decoded_size = 1111 (for smallest), 0101, 0001 (for largest)
-      val sizeOH1 = UIntToOH1(edge.size(in), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
-      val decoded_size = Seq.tabulate(ratio) { i => trailingZeros(i).map(!sizeOH1(_)).getOrElse(Bool(true)) }
-
-      val first = filter(ratio-1)
-      val new_filter = Mux(first, Cat(decoded_size.reverse), filter << 1)
-      val last = new_filter(ratio-1) || !hasData
-      when (fire) {
-        filter := new_filter 
-        when (!hasData) { filter := SInt(-1, width = ratio).asUInt }
-      }
-
-      if (edge.staticHasData(in) == Some(false)) {
-        (Bool(true), UInt(0), UInt(0))
-      } else {
-        val select = Cat(mask.reverse) & new_filter
-        (last, Mux1H(select, dataSlices), Mux1H(select, maskSlices))
-      }
-    }
-
-    def merge(edge: TLEdge, in: TLDataChannel, fire: Bool): (Bool, UInt) = {
-      val count = RegInit(UInt(0, width = log2Ceil(ratio)))
-      val rdata = Reg(UInt(width = (ratio-1)*outerBeatBytes*8))
-      val data = Cat(edge.data(in), rdata)
-      val first = count === UInt(0)
-      val limit = UIntToOH1(edge.size(in), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
-      val last = count === limit || !edge.hasData(in)
-
-      when (fire) {
-        rdata := data >> outerBeatBytes*8
-        count := count + UInt(1)
-        when (last) { count := UInt(0) }
-      }
-
-      val cases = Seq.tabulate(log2Ceil(ratio)+1) { i =>
-        val high = innerBeatBytes*8
-        val take = (1 << i)*outerBeatBytes*8
-        Fill(1 << (log2Ceil(ratio)-i), data(high-1, high-take))
-      }
-      val mux = Vec.tabulate(log2Ceil(edge.maxTransfer)+1) { lgSize =>
-        cases(min(max(lgSize - log2Ceil(outerBeatBytes), 0), log2Ceil(ratio)))
-      }
-
-      if (edge.staticHasData(in) == Some(false)) {
-        (Bool(true), UInt(0))
-      } else {
-        (last, mux(edge.size(in)))
-      }
-    }
-
-    val in = io.in(0)
-    val out = io.out(0)
-
-    val (alast, adata, amask) = split(edgeIn, in.a.bits, out.a.fire())
-    in.a.ready := out.a.ready && alast
-    out.a.valid := in.a.valid
-    out.a.bits := in.a.bits
-    out.a.bits.addr_hi := Cat(in.a.bits.addr_hi, edgeIn.addr_lo(in.a.bits) >> log2Ceil(outerBeatBytes))
-    out.a.bits.data := adata
-    out.a.bits.mask := amask
-
-    val (dlast, ddata) = merge(edgeOut, out.d.bits, out.d.fire())
-    out.d.ready := in.d.ready || !dlast
-    in.d.valid := out.d.valid && dlast
-    in.d.bits := out.d.bits
-    in.d.bits.data := ddata
-
-    if (bce) {
-      require (false)
-      // C has no wmask !!!
-//      val (clast, cdata, cmask) = split(in.c.bits, out.c.fire())
-//      in.c.ready := out.c.ready && clast
-//      out.c.valid := in.c.valid
-//      out.c.bits := in.c.bits
-//      out.c.bits.data := cdata
-//      out.c.bits.mask := cmask
-
-      in.e.ready := out.e.ready
-      out.e.valid := in.e.valid
-      out.e.bits := in.e.bits
-    } else {
-      in.b.valid := Bool(false)
-      in.c.ready := Bool(true)
-      in.e.ready := Bool(true)
-      out.b.ready := Bool(true)
-      out.c.valid := Bool(false)
-      out.e.valid := Bool(false)
-    }
-  }
-}
-
-object TLNarrower
-{
-  // applied to the TL source node; connect (Narrower(x.node, 16) -> y.node)
-  def apply(x: TLBaseNode, innerBeatBytes: Int)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
-    val narrower = LazyModule(new TLNarrower(innerBeatBytes))
-    lazyModule.connect(x -> narrower.node)
-    narrower.node
-  }
-}

src/main/scala/uncore/tilelink2/Nodes.scala

@@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.SourceInfo
 // PO = PortOutputParameters
 // EI = EdgeInput
 // EO = EdgeOutput
-abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
+abstract class NodeImp[PO, PI, EO, EI, B <: Data]
 {
   def edgeO(po: PO, pi: PI): EO
   def edgeI(po: PO, pi: PI): EI
@@ -19,36 +19,56 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
   def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit
 }
 
-class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
-  private val oFn: Option[Seq[PO] => PO],
-  private val iFn: Option[Seq[PI] => PI],
+class RootNode
+{
+  // You cannot create a Node outside a LazyModule!
+  require (!LazyModule.stack.isEmpty)
+
+  val lazyModule = LazyModule.stack.head
+  lazyModule.nodes = this :: lazyModule.nodes
+}
+
+class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
+  private val oFn: (Int, Seq[PO]) => Seq[PO],
+  private val iFn: (Int, Seq[PI]) => Seq[PI],
   private val numPO: Range.Inclusive,
-  private val numPI: Range.Inclusive)
+  private val numPI: Range.Inclusive) extends RootNode
 {
   // At least 0 ports must be supported
-  require (!numPO.isEmpty)
-  require (!numPI.isEmpty)
-  require (numPO.start >= 0)
-  require (numPI.start >= 0)
+  def name = lazyModule.name + "." + getClass.getName.split('.').last
+  require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
+  require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
+  require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
+  require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
 
   val noOs = numPO.size == 1 && numPO.contains(0)
   val noIs = numPI.size == 1 && numPI.contains(0)
 
-  require (noOs || oFn.isDefined)
-  require (noIs || iFn.isDefined)
-
-  private val accPO = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
-  private val accPI = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
+  private val accPO = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
+  private val accPI = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
   private var oRealized  = false
   private var iRealized = false
 
-  private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() }
-  private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() }
-  private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
-  private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
+  private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
+  private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
+  protected def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
 
-  lazy val edgesOut = oPorts.map { n => imp.edgeO(oParams.get, n.iParams.get) }
-  lazy val edgesIn  = iPorts.map { n => imp.edgeI(n.oParams.get, iParams.get) }
+  private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
+  private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
+
+  private lazy val oParams : Seq[PO] = {
+    val o = oFn(oPorts.size, iPorts.map{ case (i, n) => n.oParams(i) })
+    reqE(oPorts.size, o.size)
+    o
+  }
+  private lazy val iParams : Seq[PI] = {
+    val i = iFn(iPorts.size, oPorts.map{ case (o, n) => n.iParams(o) })
+    reqE(i.size, iPorts.size)
+    i
+  }
+
+  lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => imp.edgeO(o, n.iParams(i)) }
+  lazy val edgesIn  = (iPorts zip iParams).map { case ((o, n), i) => imp.edgeI(n.oParams(o), i) }
 
   lazy val bundleOut = imp.bundleO(edgesOut)
   lazy val bundleIn  = imp.bundleI(edgesIn)
@@ -56,53 +76,55 @@ class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
   def connectOut = bundleOut
   def connectIn = bundleIn
 
-  // source.edge(sink)
-  protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
-    require (!noOs)
-    require (!oRealized)
-    require (!x.noIs)
-    require (!x.iRealized)
+  protected[tilelink2] def := (y: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
+    val x = this // x := y
+    val info = sourceLine(sourceInfo, " at ", "")
+    require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
+    require (!y.noOs, s"${y.name}${y.lazyModule.line} was incorrectly connected as a source" + info)
+    require (!y.oRealized, s"${y.name}${y.lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
+    require (!x.noIs, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink" + info)
+    require (!x.iRealized, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
     val i = x.accPI.size
-    val o = accPO.size
-    accPO += x
-    x.accPI += this
-    () => {
-      imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
-    }
+    val o = y.accPO.size
+    y.accPO += ((i, x))
+    x.accPI += ((o, y))
+    LazyModule.stack.head.bindings = (() => {
+      imp.connect(y.connectOut(o), y.edgesOut(o), x.connectIn(i), x.edgesIn(i))
+    }) :: LazyModule.stack.head.bindings
   }
 }
 
-class IdentityNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
-  extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
+class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
+  extends BaseNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
 
-class OutputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
+class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
 {
   override def connectOut = bundleOut
   override def connectIn  = bundleOut
 }
 
-class InputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
+class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
 {
   override def connectOut = bundleIn
   override def connectIn  = bundleIn
 }
 
-class SourceNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
-  extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0)
+class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
+  extends BaseNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
 {
-  require (num.end >= 1)
+  require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
 }
 
-class SinkNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
-  extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num)
+class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
+  extends BaseNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
 {
-  require (num.end >= 1)
+  require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
 }
 
-class InteriorNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
+class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
   (oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
-  extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI)
+  extends BaseNode(imp)({case (n,s) => Seq.fill(n)(oFn(s))}, {case (n,s) => Seq.fill(n)(iFn(s))}, numPO, numPI)
 {
-  require (numPO.end >= 1)
-  require (numPI.end >= 1)
+  require (numPO.end >= 1, s"${name} is an adapter which does not accept outputs${lazyModule.line}")
+  require (numPI.end >= 1, s"${name} is an adapter which does not accept inputs${lazyModule.line}")
 }

src/main/scala/uncore/tilelink2/RegField.scala

@@ -4,6 +4,8 @@ package uncore.tilelink2
 
 import Chisel._
 
+import uncore.util.{SimpleRegIO}
+
 case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
 object RegReadFn
 {
@@ -56,7 +58,7 @@ object RegWriteFn
     })
   // write to a DecoupledIO (only safe if there is a consistent sink draining data)
   implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready })
-  // updates a register
+  // updates a register (or adds a mux to a wire)
   implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; Bool(true) })
   // noop
   implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { Bool(true) })
@@ -73,13 +75,29 @@ object RegField
   type Map = (Int, Seq[RegField])
   def apply(n: Int)            : RegField = apply(n, (), ())
   def apply(n: Int, rw: UInt)  : RegField = apply(n, rw, rw)
-  def R(n: Int, r: RegReadFn)  : RegField = apply(n, r, ())
-  def W(n: Int, w: RegWriteFn) : RegField = apply(n, (), w)
+  def r(n: Int, r: RegReadFn)  : RegField = apply(n, r, ())
+  def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w)
+
+  // This RegField allows 'set' to set bits in 'reg'.
+  // and to clear bits when the bus writes bits of value 1.
+  // Setting takes priority over clearing.
+  def w1ToClear(n: Int, reg: UInt, set: UInt): RegField =
+    RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) }))
+
+  // This RegField wraps an explicit register
+  // (e.g. Black-Boxed Register) to create a R/W register.
+  def rwReg(n: Int, bb: SimpleRegIO) : RegField =
+    RegField(n, bb.q, RegWriteFn((valid, data) => {
+      bb.en := valid
+      bb.d := data
+      Bool(true)
+    }))
 }
 
 trait HasRegMap
 {
   def regmap(mapping: RegField.Map*): Unit
+  val interrupts: Vec[Bool]
 }
 
 // See GPIO.scala for an example of how to use regmap

src/main/scala/uncore/tilelink2/RegisterRouter.scala

@@ -75,29 +75,39 @@ object TLRegisterNode
 // register mapped device from a totally abstract register mapped device.
 // See GPIO.scala in this directory for an example
 
-abstract class TLRegisterRouterBase(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends LazyModule
+abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int) extends LazyModule
 {
   val node = TLRegisterNode(address, concurrency, beatBytes)
+  val intnode = IntSourceNode(name + s" @ ${address.base}", interrupts)
 }
 
-class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
+case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])
 
-class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
+class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
+{
+  val interrupts = arg.interrupts
+  val in = arg.in
+}
+
+class TLRegBundle[P](val params: P, arg: TLRegBundleArg) extends TLRegBundleBase(arg)
+
+class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
   extends LazyModuleImp(router) with HasRegMap
 {
   val io = bundleBuilder
+  val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
   def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
 }
 
-class TLRegisterRouter[B <: Bundle, M <: LazyModuleImp]
-   (base: BigInt, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
-   (bundleBuilder: Vec[TLBundle] => B)
+class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp]
+   (base: BigInt, interrupts: Int = 0, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
+   (bundleBuilder: TLRegBundleArg => B)
    (moduleBuilder: (=> B, TLRegisterRouterBase) => M)
-  extends TLRegisterRouterBase(AddressSet(base, size-1), concurrency, beatBytes)
+  extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes)
 {
   require (size % 4096 == 0) // devices should be 4K aligned
   require (isPow2(size))
   require (size >= 4096)
 
-  lazy val module = moduleBuilder(bundleBuilder(node.bundleIn), this)
+  lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
 }

src/main/scala/uncore/tilelink2/SRAM.scala

@@ -59,13 +59,14 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
       d_size   := in.a.bits.size
       d_source := in.a.bits.source
       d_addr   := edge.addr_lo(in.a.bits)
-      when (read) {
-        rdata := mem.read(memAddress)
-      } .otherwise {
-        mem.write(memAddress, wdata, in.a.bits.mask.toBools)
-      }
     }
 
+    // exactly this pattern is required to get a RWM memory
+    when (in.a.fire() && !read) {
+      mem.write(memAddress, wdata, in.a.bits.mask.toBools)
+    }
+    rdata := mem.read(memAddress, in.a.fire() && read)
+
     // Tie off unused channels
     in.b.valid := Bool(false)
     in.c.ready := Bool(true)

src/main/scala/uncore/tilelink2/WidthWidget.scala

@@ -0,0 +1,180 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+import chisel3.internal.sourceinfo.SourceInfo
+import scala.math.{min,max}
+
+// innBeatBytes => the new client-facing bus width
+class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
+{
+  val node = TLAdapterNode(
+    clientFn  = { case Seq(c) => c },
+    managerFn = { case Seq(m) => m.copy(beatBytes = innerBeatBytes) })
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in  = node.bundleIn
+      val out = node.bundleOut
+    }
+
+    def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
+      val inBytes = edgeIn.manager.beatBytes
+      val outBytes = edgeOut.manager.beatBytes
+      val ratio = outBytes / inBytes
+
+      val rdata = Reg(UInt(width = (ratio-1)*inBytes*8))
+      val rmask = Reg(UInt(width = (ratio-1)*inBytes))
+      val data = Cat(edgeIn.data(in.bits), rdata)
+      val mask = Cat(edgeIn.mask(in.bits), rmask)
+      val size = edgeIn.size(in.bits)
+      val hasData = edgeIn.hasData(in.bits)
+      val addr_lo = in.bits match {
+        case x: TLAddrChannel => edgeIn.address(x)
+        case _ => UInt(0)
+      }
+      val addr = addr_lo >> log2Ceil(outBytes)
+
+      val count = RegInit(UInt(0, width = log2Ceil(ratio)))
+      val first = count === UInt(0)
+      val limit = UIntToOH1(size, log2Ceil(outBytes)) >> log2Ceil(inBytes)
+      val last = count === limit || !hasData
+
+      when (in.fire()) {
+        rdata := data >> inBytes*8
+        rmask := mask >> inBytes
+        count := count + UInt(1)
+        when (last) { count := UInt(0) }
+      }
+
+      val cases = Seq.tabulate(log2Ceil(ratio)+1) { i =>
+        val high = outBytes
+        val take = (1 << i)*inBytes
+        (Fill(1 << (log2Ceil(ratio)-i), data(high*8-1, (high-take)*8)),
+         Fill(1 << (log2Ceil(ratio)-i), mask(high  -1, (high-take))))
+      }
+      val dataMux = Vec.tabulate(log2Ceil(edgeIn.maxTransfer)+1) { lgSize =>
+        cases(min(max(lgSize - log2Ceil(inBytes), 0), log2Ceil(ratio)))._1
+      }
+      val maskMux = Vec.tabulate(log2Ceil(edgeIn.maxTransfer)+1) { lgSize =>
+        cases(min(max(lgSize - log2Ceil(inBytes), 0), log2Ceil(ratio)))._2
+      }
+
+      val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else dataMux(size)
+      val maskOut = maskMux(size) & edgeOut.mask(addr_lo, size)
+
+      in.ready := out.ready || !last
+      out.valid := in.valid && last
+      out.bits := in.bits
+      edgeOut.data(out.bits) := dataOut
+
+      out.bits match {
+        case a: TLBundleA => a.addr_hi := addr; a.mask := maskOut
+        case b: TLBundleB => b.addr_hi := addr; b.mask := maskOut
+        case c: TLBundleC => c.addr_hi := addr; c.addr_lo := addr_lo
+        case d: TLBundleD => ()
+          // addr_lo gets padded with 0s on D channel, the only lossy transform in this core
+          // this should be safe, because we only care about addr_log on D to determine which
+          // piece of data to extract when the D data bus is narrowed. Since we duplicated the
+          // data to all locations, addr_lo still points at a valid copy.
+      }
+    }
+
+    def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
+      val inBytes = edgeIn.manager.beatBytes
+      val outBytes = edgeOut.manager.beatBytes
+      val ratio = inBytes / outBytes
+
+      val hasData = edgeIn.hasData(in.bits)
+      val size = edgeIn.size(in.bits)
+      val data = edgeIn.data(in.bits)
+      val mask = edgeIn.mask(in.bits)
+      val addr = in.bits match {
+        case x: TLAddrChannel => edgeIn.address(x) >> log2Ceil(outBytes)
+        case _ => UInt(0)
+      }
+
+      val dataSlices = Vec.tabulate(ratio) { i => data((i+1)*outBytes*8-1, i*outBytes*8) }
+      val maskSlices = Vec.tabulate(ratio) { i => mask((i+1)*outBytes  -1, i*outBytes)   }
+      val filter = Reg(UInt(width = ratio), init = SInt(-1, width = ratio).asUInt)
+      val maskR = maskSlices.map(_.orR)
+
+      // decoded_size = 1111 (for smallest), 0101, 0001 (for largest)
+      val sizeOH1 = UIntToOH1(size, log2Ceil(inBytes)) >> log2Ceil(outBytes)
+      val decoded_size = Seq.tabulate(ratio) { i => trailingZeros(i).map(!sizeOH1(_)).getOrElse(Bool(true)) }
+
+      val first = filter(ratio-1)
+      val new_filter = Mux(first, Cat(decoded_size.reverse), filter << 1)
+      val last = new_filter(ratio-1) || !hasData
+      when (out.fire()) {
+        filter := new_filter 
+        when (!hasData) { filter := SInt(-1, width = ratio).asUInt }
+      }
+
+      val select = Cat(maskR.reverse) & new_filter
+      val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else Mux1H(select, dataSlices)
+      val maskOut = Mux1H(select, maskSlices)
+
+      in.ready := out.ready && last
+      out.valid := in.valid
+      out.bits := in.bits
+      edgeOut.data(out.bits) := dataOut
+
+      out.bits match {
+        case a: TLBundleA => a.addr_hi := addr; a.mask := maskOut
+        case b: TLBundleB => b.addr_hi := addr; b.mask := maskOut
+        case c: TLBundleC => c.addr_hi := addr
+        case d: TLBundleD => ()
+      }
+
+      // addr_lo gets truncated automagically
+    }
+    
+    def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
+      if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
+        // nothing to do; pass it through
+        out <> in
+      } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
+        // split input to output
+        split(edgeIn, in, edgeOut, out)
+      } else {
+        // merge input to output
+        merge(edgeIn, in, edgeOut, out)
+      }
+    }
+
+    val edgeOut = node.edgesOut(0)
+    val edgeIn = node.edgesIn(0)
+    val in = io.in(0)
+    val out = io.out(0)
+
+    splice(edgeIn,  in.a,  edgeOut, out.a)
+    splice(edgeOut, out.d, edgeIn,  in.d)
+
+    if (edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe) {
+      splice(edgeOut, out.b, edgeIn,  in.b)
+      splice(edgeIn,  in.c,  edgeOut, out.c)
+      in.e.ready := out.e.ready
+      out.e.valid := in.e.valid
+      out.e.bits := in.e.bits
+    } else {
+      in.b.valid := Bool(false)
+      in.c.ready := Bool(true)
+      in.e.ready := Bool(true)
+      out.b.ready := Bool(true)
+      out.c.valid := Bool(false)
+      out.e.valid := Bool(false)
+    }
+  }
+}
+
+object TLWidthWidget
+{
+  // applied to the TL source node; y.node := WidthWidget(x.node, 16)
+  def apply(x: TLBaseNode, innerBeatBytes: Int)(implicit sourceInfo: SourceInfo): TLBaseNode = {
+    val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
+    widget.node := x
+    widget.node
+  }
+}

src/main/scala/uncore/tilelink2/package.scala

@@ -1,10 +1,18 @@
 package uncore
 
 import Chisel._
+import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
 
 package object tilelink2
 {
   type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
+  type IntBaseNode = BaseNode[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
   def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
   def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
+  def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
+
+  def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
+    case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
+    case _ => ""
+  }
 }

src/main/scala/uncore/util/BlackBoxRegs.scala

@@ -0,0 +1,83 @@
+package uncore.util
+
+import Chisel._
+
+import cde.{Parameters}
+
+/** This black-boxes an Async Reset
+  * Reg.
+  *  
+  * Because Chisel doesn't support
+  * parameterized black boxes, 
+  * we unfortunately have to 
+  * instantiate a number of these.
+  *  
+  *  Do not confuse an asynchronous
+  *  reset signal with an asynchronously
+  *  reset reg. You should still 
+  *  properly synchronize your reset 
+  *  deassertion.
+  *  
+  *  @param d Data input
+  *  @param q Data Output
+  *  @param clk Clock Input
+  *  @param rst Reset Input
+  *  
+  *  @param init Value to write at Reset. 
+  *  This is a constant, 
+  *  but this construction
+  *  will likely make backend flows
+  *  and lint tools unhappy.
+  * 
+  */
+
+class AsyncResetReg  extends BlackBox {
+
+  val io = new Bundle {
+    val d = Bool(INPUT)
+    val q = Bool(OUTPUT)
+
+    val clk = Clock(INPUT)
+    val rst = Bool(INPUT)
+
+    val init = Bool(INPUT)
+  }
+
+}
+
+
+class SimpleRegIO(val w: Int) extends Bundle{
+
+  val d = UInt(INPUT, width = w)
+  val q = UInt(OUTPUT, width = w)
+
+  val en = Bool(INPUT)
+
+}
+
+class AsyncResetRegVec(val w: Int, val init: Int) extends Module {
+
+  val io = new SimpleRegIO(w)
+
+  val bb_q = Wire(UInt(width = w))
+  val bb_d = Wire(UInt(width = w))
+
+  val init_val = Wire(UInt(width = w))
+  init_val := UInt(init, width = w)
+
+  val async_regs = List.fill(w)(Module (new AsyncResetReg))
+
+  bb_q := (async_regs.map(_.io.q)).asUInt()
+  bb_d := Mux(io.en , io.d , bb_q)
+
+  io.q := bb_q
+
+  
+  for ((reg, idx) <- async_regs.zipWithIndex) {
+    reg.io.clk := clock
+    reg.io.rst := reset
+    reg.io.init := init_val(idx)
+    reg.io.d := bb_d(idx)
+  }
+
+}

vsim/Makefrag

@@ -6,7 +6,8 @@
 
 bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
 	$(base_dir)/vsrc/jtag_vpi.v \
-	$(base_dir)/vsrc/AsyncMailbox.v
+	$(base_dir)/vsrc/AsyncMailbox.v \
+	$(base_dir)/vsrc/AsyncResetReg.v
 
 sim_vsrcs = \
 	$(generated_dir)/$(MODEL).$(CONFIG).v \

vsrc/AsyncResetReg.v

@@ -0,0 +1,51 @@
+
+
+/** This black-boxes an Async Reset
+  * Reg.
+  *  
+  * Because Chisel doesn't support
+  * parameterized black boxes, 
+  * we unfortunately have to 
+  * instantiate a number of these.
+  *  
+  *  Do not confuse an asynchronous
+  *  reset signal with an asynchronously
+  *  reset reg. You should still 
+  *  properly synchronize your reset 
+  *  deassertion.
+  *  
+  *  @param d Data input
+  *  @param q Data Output
+  *  @param clk Clock Input
+  *  @param rst Reset Input
+  *  
+  *  @param init Value to write at Reset. 
+  *  This is a constant, 
+  *  but this construction
+  *  will likely make backend flows
+  *  and lint tools unhappy.
+  * 
+  */
+
+module AsyncResetReg (
+                      input      d,
+                      output reg q,
+
+                      input      clk,
+                      input      rst,
+                      
+                      input      init);
+
+   always @(posedge clk or posedge rst) begin
+
+      if (rst) begin
+         q <= init;
+      end else begin
+         q <= d;
+      end
+   
+   end
+   
+
+endmodule // AsyncResetReg
+