riscv/rocket-chip
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  • f1130b2faf Merge pull request #812 from freechipsproject/bump-tools Scott Johnson 2017-06-22 08:40:00 -07:00
  • a7273bccbe Bump riscv-tools to get new riscv-isa-sim Scott Johnson 2017-06-21 22:34:25 -07:00
  • 0fdaa28694 Merge pull request #811 from freechipsproject/isp-tweaks Henry Cook 2017-06-20 19:24:28 -07:00
  • bf431c0a53 groundtest: fix test ram width Henry Cook 2017-06-20 18:05:08 -07:00
  • 2f2fe0a973 clint: don't ask for what you know (nTiles) Wesley W. Terpstra 2017-06-20 17:21:53 -07:00
  • 1c97a2a94c allow re-positionable PLIC and Clint, and change coreplex internal network names Henry Cook 2017-06-20 16:11:57 -07:00
  • 5552f23294 tims: explictly name them for generated address map Henry Cook 2017-06-16 12:55:59 -07:00
  • 6b79842e66 dcache: just left shift by untagbits to get tag Henry Cook 2017-06-15 18:09:23 -07:00
  • 7521050a48 Merge pull request #810 from freechipsproject/isp-fixes Henry Cook 2017-06-20 16:35:06 -07:00
  • bb309e573f TLSplitter: special-case the case of no split necessary Wesley W. Terpstra 2017-06-20 14:10:25 -07:00
  • 53f030c037 TLSplitter: default policy is roundRobin Wesley W. Terpstra 2017-06-20 14:03:01 -07:00
  • 1aa4f5ce33 TLSplitter: QoR improvements Wesley W. Terpstra 2017-06-20 14:01:07 -07:00
  • f6e0dd12c8 TLSplitter: ManagerUnification is not used in Xbars Wesley W. Terpstra 2017-06-20 13:58:30 -07:00
  • f396b4142d Merge pull request #806 from freechipsproject/mulh Andrew Waterman 2017-06-20 13:01:16 -07:00
  • 675f183dd2 refactor ICache to be reusable by other frontends (#808) Colin Schmidt 2017-06-20 08:21:01 -07:00
  • a6d9884cc0 Improve integer mul/div Andrew Waterman 2017-06-19 12:07:19 -07:00
  • ff1f0170dc changing SystemVerilog params to Verilog style (#801) Shreesha Srinath 2017-06-16 22:47:12 -07:00
  • 31415060fe Merge pull request #802 from freechipsproject/fix-decode-of-instruction-after-ebreak Richard Xia 2017-06-16 15:07:24 -07:00
  • 61c39da475 Check for rvc before declaring illegal instruction after an ebreak. Richard Xia 2017-06-15 19:49:59 -07:00
  • d0f8cdd00c Merge pull request #804 from freechipsproject/travis_cache_stages Megan Wachs 2017-06-16 07:31:56 -07:00
  • a89c0551b7 travis: use travis_wait again Wesley W. Terpstra 2017-06-15 23:04:17 -07:00
  • 30a3e3ef55 travis: attempt to make 2 build stages for cache Megan Wachs 2017-06-15 21:31:15 -07:00
  • 93d423d202 diplomacy: optimize IdRange.contains (#798) Wesley W. Terpstra 2017-06-15 15:56:14 -07:00
  • 4059d9417f GeneratorUtils: support to elaborate a RawModule Shreesha Srinath 2017-06-15 14:33:02 -07:00
  • d316aeb275 Merge pull request #799 from freechipsproject/bump-riscv-tools-start-multiple-harts Megan Wachs 2017-06-15 13:55:46 -07:00
  • 5368ea60fe Merge pull request #757 from freechipsproject/isp-port Henry Cook 2017-06-15 13:07:19 -07:00
  • 9a789fc0cf Bump riscv-tools to pick up FESVR which allows starting all harts Megan Wachs 2017-06-15 11:05:07 -07:00
  • 2665a3eb2f Bump firrtl (#797) Jack Koenig 2017-06-15 10:06:24 -07:00
  • c259e39fa3 Merge pull request #796 from freechipsproject/buffer-instance Wesley W. Terpstra 2017-06-14 15:58:29 -07:00
  • 1f8c4ba4ca CoreplexNetwork: don't force a buffer on the coherence manager Wesley W. Terpstra 2017-06-14 14:27:23 -07:00
  • 4a15d47061 diplomacy: BufferParams can now directly create a Queue Wesley W. Terpstra 2017-06-14 13:45:12 -07:00
  • 36562ce48e Merge pull request #794 from freechipsproject/xbar-debug Wesley W. Terpstra 2017-06-13 19:44:28 -07:00
  • c85486e67c travis: don't give up if gcc is slow to build riscv-tools Wesley W. Terpstra 2017-06-13 16:57:37 -07:00
  • b4b165112c PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave Wesley W. Terpstra 2017-06-13 16:04:57 -07:00
  • 94f85e8bc8 tilelink2: TLMonitor will not create giant wires Wesley W. Terpstra 2017-06-13 15:35:22 -07:00
  • 8264c0a77e add a debug print for xbar id mappings Colin Schmidt 2017-06-13 14:32:35 -07:00
  • 8278d22fcd Merge pull request #776 from freechipsproject/lazy-raw-module-imp Henry Cook 2017-06-13 15:50:12 -07:00
  • 80a3278139 travis: travis_wait to 80 Henry Cook 2017-06-13 14:24:40 -07:00
  • 9bbde9767c rocketchip: top-level systems are now multi-IO modules Henry Cook 2017-06-01 16:06:36 -07:00
  • 2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules Henry Cook 2017-05-02 01:36:38 -07:00
  • 4a24e9a6c6 Merge pull request #792 from freechipsproject/fix-fdiv Andrew Waterman 2017-06-09 18:27:19 -07:00
  • 76af15a6ff Fix FPU control bug for div/sqrt Andrew Waterman 2017-06-09 13:35:38 -07:00
  • e69badb205 Merge pull request #791 from freechipsproject/tlb Andrew Waterman 2017-06-09 15:49:25 -07:00
  • 8552c77972 Fix I$ reset regression FU-357 Andrew Waterman 2017-06-08 17:46:37 -07:00
  • 0812f9387d Bump firrtl to get performance bug fixes (#790) Jack Koenig 2017-06-08 17:39:21 -04:00
  • 5a4daebbcc minNum -> minimumNumber (#766) Andrew Waterman 2017-06-08 11:12:52 -07:00
  • 8cb250cfe6 Fix FMUL sign, again (#789) Andrew Waterman 2017-06-08 01:50:00 -07:00
  • 60c896b48c Typo: is should be if ? (#786) Leway Colin 2017-06-08 01:40:13 +08:00
  • d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix Andrew Waterman 2017-06-06 00:46:03 -07:00
  • f0a59a81c8 Merge pull request #783 from freechipsproject/plusarg_docstring Megan Wachs 2017-06-05 18:21:07 -07:00
  • 07ad9203ff Fix FMUL sign of zero Andrew Waterman 2017-06-05 17:25:27 -07:00
  • 8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring Megan Wachs 2017-06-05 17:23:44 -07:00
  • 87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) Wesley W. Terpstra 2017-06-05 16:54:00 -07:00
  • 7afd5e6070 remove unnecessary whitespace. Fix grammar. Megan Wachs 2017-06-05 16:18:57 -07:00
  • 8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. Megan Wachs 2017-06-05 16:16:52 -07:00
  • 274d908d98 Changed TLXbar arbitration policy to roundRobin (#781) solomatnikov 2017-06-05 10:20:28 -07:00
  • efce8f06b8 Merge pull request #769 from freechipsproject/new-div-sqrt Andrew Waterman 2017-06-03 03:58:52 -07:00
  • 16ecbdd5b2 Reduce fanout on critical I$ miss signal Andrew Waterman 2017-06-02 14:52:52 -07:00
  • 27b143013f Improve ITLB QoR Andrew Waterman 2017-06-02 14:47:54 -07:00
  • 0ffb2c8baf Simplify and improve QoR of ShiftQueue Andrew Waterman 2017-06-01 02:22:18 -07:00
  • 8229bdee03 Remove FP unboxing from FMA critical path Andrew Waterman 2017-05-31 14:57:56 -07:00
  • 7504b47bbe Improve code quality in FP->FP and Int->FP units Andrew Waterman 2017-05-31 14:53:46 -07:00
  • 84c4ae775f Improve QoR for FP->Int conversions Andrew Waterman 2017-05-30 16:51:35 -07:00
  • 07968df183 Refactor FP Classify Andrew Waterman 2017-05-30 16:51:21 -07:00
  • 6ecd58a977 Incorporate new div/sqrt unit Andrew Waterman 2017-05-24 19:05:50 -07:00
  • b1917e7915 coreplex: add an ISPPort trait to add cross-connect points Wesley W. Terpstra 2017-05-19 18:13:53 -07:00
  • 81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 Wesley W. Terpstra 2017-05-19 17:55:57 -07:00
  • d002cec6ac NodeNumberer: add an adapter to map inter-chip fabrics Wesley W. Terpstra 2017-05-19 17:46:13 -07:00
  • 5a2a6b0386 diplomacy: add a CustomNode type that allows direct overload of methods Wesley W. Terpstra 2017-05-19 17:29:22 -07:00
  • fed1f53afa tilelink2: add a TLSplitter to be used for the ISP port Wesley W. Terpstra 2017-05-19 16:09:57 -07:00
  • a4bf678954 tilelink2: fix latent Xbar truncation bug Wesley W. Terpstra 2017-05-19 15:11:48 -07:00
  • ce12a64f4b tilelink2: support SplitterNodes Wesley W. Terpstra 2017-05-19 14:55:04 -07:00
  • de39af7f65 tilelink2: make some Xbar methods reusable Wesley W. Terpstra 2017-05-19 14:48:00 -07:00
  • 0a2a93c27d diplomacy: add the new Splitter node type Wesley W. Terpstra 2017-05-19 14:34:54 -07:00
  • c695237050 diplomacy: make :=* and :*= resolution more flexible Wesley W. Terpstra 2017-05-19 12:52:01 -07:00
  • 4679545b60 travis: front-load the longer running tests and tolerate no output (#779) Wesley W. Terpstra 2017-06-02 20:41:26 -07:00
  • cdbf67be68 Add a note to wire up jtag_mfr_id (#778) edwardcwang 2017-06-02 18:53:14 -07:00
  • 63b1f4f047 Merge pull request #777 from freechipsproject/print-axi-ids Wesley W. Terpstra 2017-06-02 18:52:55 -07:00
  • e0741a2097 axi4: don't map unused masters into TL source ID space Wesley W. Terpstra 2017-06-02 16:30:16 -07:00
  • 6b7a9f0c95 Revert "Bump firrtl to get performance bug fixes (#772)" Wesley W. Terpstra 2017-06-02 15:52:32 -07:00
  • 80c63c0da6 rocket: include hartid in cache master names Wesley W. Terpstra 2017-06-02 15:29:30 -07:00
  • d25ad10592 diplomacy: require masters to have a name Wesley W. Terpstra 2017-06-02 15:09:35 -07:00
  • 475ac93cdf coreplex: print memory map using DTS, also write a JSON for it Wesley W. Terpstra 2017-06-02 13:53:22 -07:00
  • ae8734da05 diplomacy: report cacheability in ResourceAddress Wesley W. Terpstra 2017-06-01 23:25:26 -07:00
  • 985d9750e6 tilelink2: Xbar QoR improvement Wesley W. Terpstra 2017-06-01 23:01:10 -07:00
  • 9317a00896 tilelink2: ToAXI4, sort and print AXI IDs used Wesley W. Terpstra 2017-06-01 18:34:04 -07:00
  • 38e6512c0f Merge pull request #775 from freechipsproject/unify-only-at-end Wesley W. Terpstra 2017-06-01 17:16:48 -07:00
  • eb14329c63 tilelink2: only combine managers of the same resources Wesley W. Terpstra 2017-06-01 15:29:45 -07:00
  • 1f531b1593 tilelink2: improve round robin arbiter QoR Wesley W. Terpstra 2017-06-01 15:26:04 -07:00
  • 5994714970 diplomacy: move manager unification to meta-data only Wesley W. Terpstra 2017-06-01 15:16:01 -07:00
  • 0fe625c52f diplomacy: improve PMA circuit QoR Wesley W. Terpstra 2017-06-01 14:59:53 -07:00
  • dfb6340927 Merge pull request #755 from freechipsproject/verilator-plusargs Wesley W. Terpstra 2017-06-01 14:34:09 -07:00
  • 6a7e6ab325 plusarg_reader: support verilator Wesley W. Terpstra 2017-05-18 22:54:40 -07:00
  • 9eae1fa377 verilator: bump to version 3.904 Wesley W. Terpstra 2017-05-18 22:52:28 -07:00
  • 6124bf0cc2 sort entires in the printed address map (#773) Yunsup Lee 2017-05-31 07:45:46 -10:00
  • 8e45dd9352 Bump firrtl to get performance bug fixes (#772) Jack Koenig 2017-05-30 20:21:29 -07:00
  • 8d04e0efb8 Merge pull request #771 from freechipsproject/jtag_vpi_tab Megan Wachs 2017-05-30 17:29:23 -07:00
  • 6aa13b4e01 JTAG VPI: Make it work without debug_pp flag Megan Wachs 2017-05-30 15:46:45 -07:00
  • f61e30763f Merge pull request #768 from freechipsproject/flush_jtag_vpi Megan Wachs 2017-05-26 15:51:43 -07:00
  • e3e77d68e6 PTW now does not require atomic memory operations, so take out the requirement (#767) Jacob Chang 2017-05-26 13:11:15 -07:00