Merge pull request #794 from freechipsproject/xbar-debug
Deal with lots of sources more gracefully.
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commit
36562ce48e
@ -45,7 +45,7 @@ jobs:
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include:
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- stage: prepare cache
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script:
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- make tools verilator -C regression SUITE=none
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- travis_wait 120 make tools verilator -C regression SUITE=none
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before_install:
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- export CXX=g++-4.8 CC=gcc-4.8
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before_cache:
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@ -346,7 +346,11 @@ trait HasPeripheryErrorSlave extends HasSystemNetworks {
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private val config = p(ErrorConfig)
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private val maxXfer = min(config.address.map(_.alignment).max.toInt, 4096)
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val error = LazyModule(new TLError(config.address, peripheryBusConfig.beatBytes))
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error.node := TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node)
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// Override the default Parameters to exclude the TLMonitor between the Fragmenter and error slave.
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// Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others.
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private def sourceInfo(implicit x: chisel3.internal.sourceinfo.SourceInfo) = x
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error.node.:=(TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node))(new WithoutTLMonitors ++ p, sourceInfo)
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}
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@ -466,10 +466,21 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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}
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def legalizeUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
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legalizeADSource(bundle, edge)
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if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
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val sourceBits = log2Ceil(edge.client.endSourceId)
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val tooBig = 14 // >16kB worth of flight information gets to be too much
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if (sourceBits > tooBig) {
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println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
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} else {
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legalizeADSource(bundle, edge)
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}
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if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB && edge.manager.endSinkId > 1) {
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// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
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if (edge.manager.endSinkId > 1) legalizeDESink(bundle, edge)
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val sinkBits = log2Ceil(edge.manager.endSinkId)
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if (sinkBits > tooBig) {
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println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
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} else {
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legalizeDESink(bundle, edge)
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}
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}
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}
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@ -84,7 +84,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
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val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
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val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
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// Print the mapping
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// Print the address mapping
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if (false) {
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println("Xbar mapping:")
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route_addrs.foreach { p =>
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@ -95,6 +95,15 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
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println("--")
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}
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// Print the ID mapping
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if (false) {
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println(s"XBar ${name} mapping:")
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(node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
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println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
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}
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println("")
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}
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// We need an intermediate size of bundle with the widest possible identifiers
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val wide_bundle = io.in(0).params.union(io.out(0).params)
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