riscv/rocket-chip
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Merge pull request #802 from freechipsproject/fix-decode-of-instruction-after-ebreak

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Check for rvc before declaring illegal instruction after an ebreak.
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Richard Xia 2017-06-16 15:07:24 -07:00 committed by GitHub
commit 31415060fe
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/Rocket.scala
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@ -212,7 +212,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
id_ctrl.rocc && csr.io.decode.rocc_illegal ||
id_csr_en && (csr.io.decode.read_illegal || !id_csr_ren && csr.io.decode.write_illegal) ||
(id_sfence || id_system_insn) && csr.io.decode.system_illegal
!ibuf.io.inst(0).bits.rvc && ((id_sfence || id_system_insn) && csr.io.decode.system_illegal)
// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
val id_amo_aq = id_inst(0)(26)
val id_amo_rl = id_inst(0)(25)