Merge pull request #792 from freechipsproject/fix-fdiv
Fix FPU control bug for div/sqrt
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4a24e9a6c6
@ -754,15 +754,10 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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if (cfg.divSqrt) {
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val divSqrt_killed = Reg(Bool())
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makeDivSqrt(FType.S, wb_ctrl.singleOut)
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fLen match {
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case 32 =>
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case 64 => makeDivSqrt(FType.D, !wb_ctrl.singleOut)
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}
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def makeDivSqrt(t: FType, en: Bool) = {
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for (t <- floatTypes) {
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val tag = !mem_ctrl.singleOut // TODO typeTag
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val divSqrt = Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0))
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divSqrt.io.inValid := en && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
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divSqrt.io.inValid := mem_reg_valid && tag === typeTag(t) && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
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divSqrt.io.sqrtOp := mem_ctrl.sqrt
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divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
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divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
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