732 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	fa472e38fb	tilelink2: monitor error line legality	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	edb17d1e34	tilelink2: document allowed (and required) response messages	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	ec1f901a38	tilelink2: move error from type into Bundle and add HintAck ... We need Grant with errors too. We also want to match response type to request type more easily.	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	534d7f6eb6	tilelink2: implement SRAM manager	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	32894a8e20	tilelink2: transfers must never exceed 4kB	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	dd27a60daa	tilelink2: use consistent in/out ports for TLSimpleFactories	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	1a87eef3e2	tilelink2: add atomic message types	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	5f7711a0c0	tilelink2: add an intermediate type for simple factories	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	967d8f108c	tilelink2: support ready-valid enqueue+dequeue on register fields	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	77cf186cf0	tilelink2: make bundle parameterization reusable	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	594850eaae	tilelink2: assert-fail on something more user understandable	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	dc1164a996	tilelink2: defer bundle construction until after Module base class instantiated	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	18e149098a	tilelink2: connect abstract register-based modules to TileLink	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	917a9c8e5d	tilelink2: forward declarations for message constructors	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	4649c42f50	tilelink2: use a new type in the signature of null-parameter Bundle methods	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	0ff33a31a4	tilelink2: add a stub SRAM manager	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	a87c2d13e2	tilelink2: include an abstract definition for register mapped devices	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	3a441d853f	tilelink2: clarify that fifoId only applies to accesses (not hints)	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	4b99bd3be1	tilelink2: mask out unnecessary address bits	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	e24ba61754	tilelink2: distinguish two levels of uncacheability	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	e506309998	tilelink2: prototype crossbar implementation	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	34f65938b6	tilelink2: add a TLBundle constructor	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	1cd85ff050	tilelink2: add some bundle introspection to scaffold the xbar	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	9c62f5d9c1	tilelink2: shave off a few more firrtl monitor lines	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	af29595979	tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	d7e839280f	tilelink2: include legal message monitor	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	492a38aedc	tilelink2: only accesses can have errors (release must make forward progress)	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	6599bcb77b	tilelink2: statically check Operations are remotely plausible	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	8cff45f254	tilelink2: use byte-aligned addressing ... This makes it possible to fully validate user input in a monitor. We will override the lower bits with constant 0s in the TL connect.	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	45e152e97e	tilelink2: include Operation constructors	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	5b10c1a328	tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3)	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	8592cbf0e3	tilelink2: Message and Permisison types from Henry	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	9a460322da	tilelink2: add synthesizable test methods for Parameters	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	7328b55abd	tilelink2: first cut at parameterization	2016-09-05 20:58:37 -07:00
Howard Mao	7b20609d4d	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00
Andrew Waterman	fee5d2b1ea	Remove parameters for some things that aren't parameterizable ... Heads up @colinschmidt and @ccelio. I'm removing these because they are ISA constants and so are not truly parameters, so the parameter place is not the place for them. Since BOOM and Hwacha both depend on rocket, you should be able to obtain them by instantiating/extending rocket.HasCoreParameters.	2016-08-19 12:04:13 -07:00
Howard Mao	33676e81f8	use isOneOf as much as possible	2016-08-19 09:56:06 -07:00
Howard Mao	7671811ac9	merge uncore.Util into uncore.util	2016-08-18 18:33:46 -07:00
Howard Mao	38e0967816	strip DMA and RoCC CSRs out of rocket and uncore (#201)	2016-08-15 23:08:55 -07:00
Howard Mao	571d579b86	get unit tests working again	2016-08-10 11:23:07 -07:00
Howard Mao	f95d319162	don't use secondary external address map; collapse submap instead	2016-08-09 22:29:38 -07:00
Howard Mao	405294167f	fix TL -> Nasti converter w id	2016-08-09 18:24:23 -07:00
Andrew Waterman	458520c8f6	Use a generic UInt for TileLink op sizes, rather than MT_xx enum	2016-08-09 15:24:51 -07:00
Howard Mao	0a85e92652	Allow additional internal MMIO devices to be created without changing BaseConfig	2016-08-04 11:04:52 -07:00
Andrew Waterman	791a27748b	Update firrtl and remove firrtl hack in plic	2016-08-02 15:19:48 -07:00
Howard Mao	b7723f1ff8	make unit tests local to the packages being tested	2016-08-01 17:02:00 -07:00
Andrew Waterman	fe670e5421	Stop using deprecated FileSystemUtilities to create files	2016-07-31 18:04:56 -07:00
Andrew Waterman	832e56d3c7	Fix toBits/toUInt/toSInt deprecation warnings	2016-07-31 17:13:52 -07:00
Howard Mao	f34b0b0447	make sure L2 tracker doesn't read data array again if data buffer already filled	2016-07-29 16:47:31 -07:00
Howard Mao	fbcc7317cf	make sure PseudoLRU is given power of 2 ways	2016-07-27 18:39:33 -07:00