riscv/rocket-chip
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732 Commits

Author SHA1 Message Date
Howard Mao
15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set 2016-07-27 16:47:22 -07:00
Howard Mao
82bbbf908d Fix L2 Writeback deadlock issue 
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
 2016-07-26 12:31:08 -07:00
Wesley W. Terpstra
11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter 2016-07-22 14:51:05 -07:00
Wesley W. Terpstra
a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations 2016-07-22 14:48:22 -07:00
Howard Mao
9168f35971 clean up the requirements in StatelessBridge 
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
 2016-07-21 19:41:56 -07:00
Howard Mao
12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao
c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Megan Wachs
eb9e998c08 Add ManagerToClientStatelessBridge 2016-07-21 13:49:16 -07:00
Howard Mao
0a1cd64786 fix number of builtin Acquire types 2016-07-21 13:45:20 -07:00
Howard Mao
86e31be820 fix lockup from back to back releases with data 2016-07-21 12:06:58 -07:00
Wesley W. Terpstra
fa8317fec1 debug: add clock crossing primitives 2016-07-19 14:52:43 -07:00
Henry Cook
e406d1bd73 Make probeCopy have same behavior as probeDowngrade 2016-07-18 18:22:49 -07:00
Howard Mao
9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal 2016-07-18 17:38:20 -07:00
Howard Mao
e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao
84098db81f add a TileLinkTestRAM 2016-07-15 11:03:26 -07:00
Howard Mao
b122a54c32 don't allow more outer IDs than inner IDs 2016-07-13 12:42:28 -07:00
Howard Mao
de1e25f3d1 reduce usage of CAMs in converters 2016-07-13 11:20:50 -07:00
Howard Mao
8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao
a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Andrew Waterman
70b677ecda Vec considered harmful; use isOneOf instead (#64) 
Vec is heavyweight and really should only be used for I/O and
dynamic indexing.  A recurring pattern in uncore is

    Vec(const1, const2, const3) contains x

which is nice but has a deleterious effect on simulation copilation
and execution time.  This patch proposes an alternative:

    x isOneOf (const1, const2, const3)
    x isOneOf seqOfThings

I think it's also more idiomatic.

This is just a prototype; I'm not wed to the name or implementation.
 2016-07-07 19:25:57 -07:00
Howard Mao
16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao
7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao
1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao
8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao
5d8d5e598b add buffering and locking to TL -> Nasti converter 2016-07-06 16:51:45 -07:00
Howard Mao
b10d306b4a add option to log L2 cache transactions for easier debugging 2016-07-06 14:59:09 -07:00
Howard Mao
64afc795fd make sure voluntary releases don't get allocated to L2WritebackUnit 2016-07-06 14:10:45 -07:00
Howard Mao
b105076996 fix ID mapper to disallow two in-flight requests with the same inner ID 2016-07-05 17:41:46 -07:00
Howard Mao
af76837970 conform to new NastiWriteDataChannel interface 2016-07-05 17:41:46 -07:00
Albert Ou
4c07aedfad Rewrite BRAMSlave to infer a single BRAM instance 2016-07-05 14:21:21 -07:00
Howard Mao
702444709a make sure pending bits updated for all releases 2016-07-05 12:08:22 -07:00
Howard Mao
06ed9c5794 add a single-entry queue in front of acquire and release for bufferless broadcast hub 2016-07-05 12:08:22 -07:00
Howard Mao
67bac383e3 hopefully fixed last bugs in Bufferless 2016-07-05 12:08:22 -07:00
Howard Mao
a35388bc27 fix merging of same xact ID puts/gets 2016-07-05 12:08:22 -07:00
Howard Mao
51f7bf1511 fix Bufferless voluntary release issue 2016-07-05 12:08:22 -07:00
Howard Mao
afc51c4a35 make sure TL -> NASTI converter handles multibeat transactions properly 2016-07-05 12:08:22 -07:00
Andrew Waterman
85808f8cbb Clean up PseudoLRU code 2016-07-02 15:09:12 -07:00
Howard Mao
caa9ca24b9 NASTI -> TL converter also uses ID mapper 2016-07-01 18:11:29 -07:00
Wesley W. Terpstra
39bee5198d Nasti Puts: decode wmask to determine addr_byte() and op_size() 
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
 2016-07-01 16:49:32 -07:00
Howard Mao
e163a23583 fix another bug in Widener 2016-07-01 16:24:48 -07:00
Howard Mao
10a46a36ae fix full_addr() function in TileLink 2016-07-01 15:17:41 -07:00
Howard Mao
61e3e5b45a more WIP on fixing Bufferless 2016-06-30 18:29:51 -07:00
Howard Mao
0eedffa82f WIP: Fix BufferlessBroadcastHub 2016-06-30 18:29:51 -07:00
Howard Mao
ce46f523c9 make sure Widener uses proper parameters to generate acquire/grant 2016-06-30 18:17:16 -07:00
Howard Mao
a0b1772404 change TileLinkWidthAdapter interface 2016-06-30 15:50:23 -07:00
Howard Mao
9feca99d5d make PutBlock wmask argument match Put 2016-06-28 13:10:46 -07:00
Howard Mao
b936aa9826 refactor uncore files into separate packages 2016-06-28 13:10:46 -07:00
Andrew Waterman
97e74aec3a Merge RTC and PRCI 2016-06-27 23:06:07 -07:00
Howard Mao
ec5b9dfc86 make sure trackers can handle case where there are no caching clients 2016-06-27 16:29:51 -07:00
Howard Mao
a93a70c8ec make sure merged voluntary releases are handled properly 2016-06-27 11:40:32 -07:00
Andrew Waterman
354b81c8fe Remove legacy HTIF things 
The SCR file is gone, too, because it is tightly coupled.  The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
 2016-06-23 13:17:11 -07:00
Andrew Waterman
f57524e0c1 Remove FENCE.I from debug ROM; specialize for RV64 2016-06-23 00:01:26 -07:00
Howard Mao
e3391b36b2 get rid of MuxBundle now that MuxCase and MuxLookup are fixed 2016-06-21 10:43:44 -07:00
Howard Mao
719fffff40 make sure updates from irel and iacq gated by tracker allocation 2016-06-17 17:15:02 -07:00
Howard Mao
b75b6fdcda make sure no-data voluntary releases get tracked 2016-06-17 17:15:02 -07:00
Howard Mao
ebe95fa827 fix wmask buffer clearing in L2 agents 2016-06-16 15:34:31 -07:00
Howard Mao
aba13cee7f fix BRAM slave so that it can correctly take all TileLink requests 2016-06-16 15:34:31 -07:00
Howard Mao
e716661637 make sure merged no-alloc put still allocs if original put allocs 2016-06-16 15:34:31 -07:00
Howard Mao
7e43b1d889 fix mistaken dequeueing from roq in TileLink unwrapper 2016-06-16 15:34:31 -07:00
Howard Mao
2789e60b6b fix ignt_q logic 2016-06-16 15:18:58 -07:00
Henry Cook
16bfbda3c9 Refactor the TransactionTracker logic in all the L2 TileLink Managers. 
They now share common sub-transactions within traits, and use a common
set of state transitions and scoreboarding logic. Tracker allocation
logic has also been updated. No changes to external IOs or the TileLink protocol.
A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
 2016-06-16 15:18:48 -07:00
mwachs5
2d2096e509 Add smaller ROM/RAM for 32-bit debug (#60) 2016-06-15 15:07:43 -07:00
Palmer Dabbelt
e5cfc2dac1 Add a Smi to TileLink converter (#59) 
I'm trying to get someone to attach their stuff to Rocket Chip for the
upcoming tapout.  TileLink sounded too complicated, but Smi went over
well.  Since the mmioNetwork in Rocket Chip is based on TileLink, it
seemed like the easiest thing to do was to write a TileLink to Smi
converter so people could use it.

It turns out there was already one inside the groundtest unit tests, so
I just moved that into uncore (it was inlined into a test case so you
couldn't actually use it before).  Internally the converter uses Nasti,
but I figured that's good enough for now.
 2016-06-10 14:04:28 -07:00
Megan Wachs
cee0cf345e [debug] Update Debug ROM contents to write F..F to RAM in case of exception 2016-06-09 14:05:30 -07:00
Wesley W. Terpstra
a1ebc73477 tilelink: don't accidentally make a malformed union 
Closes #55
 2016-06-09 10:44:00 -07:00
Wesley W. Terpstra
31b72625aa ahb: allow no-ops to progress also when a slave is !hready 2016-06-09 10:41:12 -07:00
Wesley W. Terpstra
7014eef339 ahb: fix bugs found using comparatortest 2016-06-09 10:41:11 -07:00
mwachs5
93c1b17b52 [debug] Remove erroneous buffer on SB read data (#56) 2016-06-08 23:31:13 -04:00
Albert Ou
5151570894 Fix valid signal for multibeat grants 2016-06-08 15:13:39 -07:00
Howard Mao
f421e2ab11 fix TileLinkWidthAdapter 2016-06-08 09:58:23 -07:00
Wesley W. Terpstra
324cabc494 tilelink: wmask was double the width it should be 
When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
 2016-06-07 14:04:01 -07:00
Howard Mao
2d66ac93d3 make sure HastiRAM cuts off the correct number of bits for word address 2016-06-06 09:26:51 -07:00
Andrew Waterman
dd85f2410f Avoid need for cloneType 2016-06-05 23:47:56 -07:00
Andrew Waterman
631e3e2dd9 Make PRCI a singleton, not per-tile 
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
 2016-06-05 23:06:21 -07:00
Andrew Waterman
be7500e4a9 Update PLIC addr map 2016-06-05 23:04:51 -07:00
Megan Wachs
b832689642 Correct Debug ROM contents 2016-06-05 19:35:25 -07:00
Megan Wachs
605fb5b92f [debug]: fix issue with subword select logic 2016-06-05 19:31:07 -07:00
Megan Wachs
3e8322816b Correct DMINFO Fields 2016-06-05 19:29:50 -07:00
Megan Wachs
7e550ab07c [debug] rocket: fix for issue 121, correct debug ROM and stall logic 2016-06-05 19:29:44 -07:00
Andrew Waterman
2e88ffc364 Cope with changes to AddrMap 2016-06-03 13:48:09 -07:00
Andrew Waterman
f1745bf142 Allow PLIC nPriorities=0 (priority fixed at 1) 2016-06-02 13:48:29 -07:00
Andrew Waterman
b7ca2145b3 Fix PLIC control bug when !grant.ready 2016-06-02 13:47:59 -07:00
Andrew Waterman
0866b4c045 Can't assign to Vec literals 2016-06-01 23:36:34 -07:00
Andrew Waterman
20e1de08da Avoid chisel2 pitfall 
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
 2016-06-01 23:35:49 -07:00
Andrew Waterman
5629fb62bf Avoid bitwise sub-assignment 2016-06-01 21:59:02 -07:00
Andrew Waterman
9518b3d589 Fix arithmetic in ROM row count 2016-06-01 21:59:02 -07:00
Andrew Waterman
8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
Wesley W. Terpstra
11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
mwachs5
740a6073f6 Add Debug Module (#49) 
* Add Debug Module

* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents

* [debug] Update Debug ROM contents to match updated addresses
 2016-06-01 16:33:33 -07:00
Howard Mao
e8408f0a8a fix HastiRAM 2016-06-01 10:33:59 -07:00
Andrew Waterman
6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Andrew Waterman
8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
Andrew Waterman
391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect 
We should eventually parameterize this, of course.
 2016-05-26 16:10:42 -07:00
Andrew Waterman
b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
Andrew Waterman
8139f71dfb Work around Chisel2 bug 
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
 2016-05-26 12:37:31 -07:00
Andrew Waterman
22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
Andrew Waterman
e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman
3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Wesley W. Terpstra
7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Andrew Waterman
c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00