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Fix toBits/toUInt/toSInt deprecation warnings

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This commit is contained in:
Andrew Waterman
2016-07-31 17:13:52 -07:00
parent a6e009d8de
commit 832e56d3c7
36 changed files with 188 additions and 171 deletions
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14
uncore/src/main/scala/Util.scala
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@ -8,4 +8,18 @@ package object Util {
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size == 1) {
x.head
} else {
val half = 1 << (log2Ceil(x.size) - 1)
val newIdx = idx & UInt(half - 1)
Mux(idx >= UInt(half), x.drop(half)(newIdx), x.take(half)(newIdx))
}
}
def asUInt(): UInt = Cat(x.map(_.asUInt).reverse)
}
}

9
uncore/src/main/scala/agents/Agents.scala
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@ -8,6 +8,7 @@ import junctions._
import uncore.tilelink._
import uncore.converters._
import uncore.coherence._
import uncore.Util._
case object NReleaseTransactors extends Field[Int]
case object NProbeTransactors extends Field[Int]
@ -59,7 +60,7 @@ trait HasCoherenceAgentWiringHelpers {
val idx = in.bits.manager_xact_id
outs.map(_.bits := in.bits)
outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && idx === UInt(i) }
in.ready := Vec(outs.map(_.ready)).read(idx)
in.ready := outs.map(_.ready).apply(idx)
}
/** Broadcasts valid messages on this channel to all trackers,
@ -82,10 +83,10 @@ trait HasCoherenceAgentWiringHelpers {
dataOverrides: Option[Seq[UInt]] = None,
allocOverride: Option[Bool] = None,
matchOverride: Option[Bool] = None) {
val ready_bits = Vec(outs.map(_.ready)).toBits
val can_alloc_bits = Vec(allocs.map(_.can)).toBits
val ready_bits = outs.map(_.ready).asUInt
val can_alloc_bits = allocs.map(_.can).asUInt
val should_alloc_bits = PriorityEncoderOH(can_alloc_bits)
val match_bits = Vec(allocs.map(_.matches)).toBits
val match_bits = allocs.map(_.matches).asUInt
val no_matches = !match_bits.orR
val alloc_ok = allocOverride.getOrElse(Bool(true))
val match_ok = matchOverride.getOrElse(Bool(true))

19
uncore/src/main/scala/agents/Cache.scala
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@ -151,9 +151,9 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
val rst = rst_cnt < UInt(nSets)
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.toSInt).toBools
val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.toSInt).toBools
val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.asSInt).toBools
val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.asSInt).toBools
when (rst) { rst_cnt := rst_cnt+UInt(1) }
val metabits = rstVal.getWidth
@ -161,21 +161,18 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
if (hasSplitMetadata) {
val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
val tags_vec = Wire(Vec(nWays, UInt(width = metabits)))
(0 until nWays).foreach { (i) =>
when (rst || (io.write.valid && wmask(i))) {
tag_arrs(i).write(waddr, wdata)
}
tags_vec(i) := tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i))
io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
}
io.resp := io.resp.fromBits(tags_vec.toBits)
} else {
val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
when (rst || io.write.valid) {
tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
}
val tags = tag_arr.read(io.read.bits.idx, io.read.valid).toBits
io.resp := io.resp.fromBits(tags)
io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
}
io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
@ -329,7 +326,7 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
val meta = Module(new MetadataArray(onReset _))
meta.io.read <> io.read
meta.io.write <> io.write
val way_en_1h = (Vec.fill(nWays){Bool(true)}).toBits
val way_en_1h = UInt((BigInt(1) << nWays) - 1)
val s1_way_en_1h = RegEnable(way_en_1h, io.read.valid)
meta.io.read.bits.way_en := way_en_1h
@ -338,7 +335,7 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
val s1_clk_en = Reg(next = io.read.fire())
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta.io.resp(w).coh.outer.isValid() && s1_way_en_1h(w).toBool).toBits
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta.io.resp(w).coh.outer.isValid() && s1_way_en_1h(w).toBool).asUInt
val s1_idx = RegEnable(io.read.bits.idx, io.read.valid) // deal with stalls?
val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
val s2_tag_match = s2_tag_match_way.orR
@ -445,7 +442,7 @@ class L2DataArray(delay: Int)(implicit p: Parameters) extends L2HellaCacheModule
val r_req = Pipe(io.read.fire(), io.read.bits)
io.resp := Pipe(r_req.valid, r_req.bits, delay)
io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren).toBits, delay).bits
io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren).asUInt, delay).bits
io.read.ready := !io.write.valid
io.write.ready := Bool(true)
}

14
uncore/src/main/scala/agents/Ecc.scala
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@ -3,6 +3,7 @@
package uncore.agents
import Chisel._
import uncore.Util._
abstract class Decoding
{
@ -63,24 +64,23 @@ class SECCode extends Code
} else
x(mapping(i))
}
Vec(y).toBits
y.asUInt
}
def decode(y: UInt) = new Decoding {
val n = y.getWidth
require(n > 0 && !isPow2(n))
val p2 = for (i <- 0 until log2Up(n)) yield 1 << i
val syndrome = p2 map { i =>
val syndrome = (p2 map { i =>
val r = for (j <- 1 to n; if (j & i) != 0)
yield y(j-1)
r reduce (_^_)
}
val s = Vec(syndrome).toBits
}).asUInt
private def swizzle(z: UInt) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
private def swizzle(z: UInt) = (1 to n).filter(i => !isPow2(i)).map(i => z(i-1)).asUInt
def uncorrected = swizzle(y)
def corrected = swizzle(((y.toUInt << 1) ^ UIntToOH(s)) >> 1)
def correctable = s.orR
def corrected = swizzle(((y << 1) ^ UIntToOH(syndrome)) >> 1)
def correctable = syndrome.orR
def uncorrectable = Bool(false)
}
private def mapping(i: Int) = i-1-log2Up(i)

4
uncore/src/main/scala/agents/StoreDataQueue.scala
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@ -52,7 +52,7 @@ trait HasStoreDataQueue extends HasStoreDataQueueParameters {
).reduce(_||_)
lazy val sdqLoc = List.fill(nTransactors) {
DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
DataQueueLocation(sdq_alloc_id, inStoreQueue).asUInt
}
/*
@ -74,7 +74,7 @@ trait HasStoreDataQueue extends HasStoreDataQueueParameters {
lazy val vwbqLoc = (0 until nTransactors).map(i =>
(DataQueueLocation(rel_data_cnt,
(if(i < nReleaseTransactors) inVolWBQueue
else inClientReleaseQueue)).toBits))
else inClientReleaseQueue)).asUInt))
/*
doInputRoutingWithAllocation(
io.inner.release,

2
uncore/src/main/scala/agents/Trackers.scala
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@ -380,7 +380,7 @@ trait EmitsInnerProbes extends HasBlockAddressBuffer
def full_representation: UInt
def initializeProbes() {
if (needs_probes)
pending_iprbs := full_representation & ~io.incoherent.toBits
pending_iprbs := full_representation & ~io.incoherent.asUInt
else
pending_iprbs := UInt(0)
}

2
uncore/src/main/scala/coherence/Directory.scala
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@ -28,7 +28,7 @@ class NullRepresentation(nClients: Int) extends DirectoryRepresentation(1) {
def one(s: UInt) = Bool(false)
def count(s: UInt) = UInt(nClients)
def next(s: UInt) = UInt(0)
def full(s: UInt) = SInt(-1, width = nClients).toUInt
def full(s: UInt) = SInt(-1, width = nClients).asUInt
}
class FullRepresentation(nClients: Int) extends DirectoryRepresentation(nClients) {

2
uncore/src/main/scala/converters/Nasti.scala
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@ -170,7 +170,7 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
val odd_outside_0 = Seq.tabulate (len/2) { i => all_outside_0(2*i+1) }
val odd_outside = odd_outside_0.reduce (_ || _)
val all_outside = all_outside_0.reduce (_ || _)
val offset = Cat(sub_offset, odd_outside.toBits)
val offset = Cat(sub_offset, odd_outside)
val size = Mux(all_outside, UInt(defsize), sub_size)
(all_outside_0, offset, size)
}

6
uncore/src/main/scala/converters/Tilelink.scala
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@ -263,8 +263,8 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
client_xact_id = put_id,
addr_block = put_block,
addr_beat = put_beat,
data = put_data.toBits,
wmask = Some(put_wmask.toBits))(outerConfig)
data = put_data.asUInt,
wmask = Some(put_wmask.asUInt))(outerConfig)
io.out.acquire.valid := sending_put || (!shrink && io.in.acquire.valid)
io.out.acquire.bits := MuxCase(get_block_acquire, Seq(
@ -505,7 +505,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
client_xact_id = gnt_client_id,
manager_xact_id = gnt_manager_id,
addr_beat = ignt_ctr.value,
data = gnt_data_buffer.toBits)(innerConfig)
data = gnt_data_buffer.asUInt)(innerConfig)
val smallget_grant = ognt.g_type === Grant.getDataBeatType

25
uncore/src/main/scala/devices/Debug.scala
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@ -224,14 +224,11 @@ case class DebugModuleConfig (
val hasHaltSum = (nComponents > 64) || (nSerialPorts > 0)
val hasDebugRom = debugRomContents match{
case Some(_) => true
case None => false
}
val hasDebugRom = debugRomContents.nonEmpty
if (hasDebugRom) {
require (debugRomContents.size > 0)
require (debugRomContents.size <= 512)
require (debugRomContents.get.size > 0)
require (debugRomContents.get.size <= 512)
}
require (nNDResetCycles > 0)
@ -647,15 +644,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
sbRamRdData := ramRdData
ramWrMask := Mux(sbRamWrEn, sbWrMask, dbRamWrMask.toBits())
ramWrMask := Mux(sbRamWrEn, sbWrMask, dbRamWrMask.asUInt)
assert (!((dbRamWrEn | dbRamRdEn) & (sbRamRdEn | sbRamWrEn)), "Stall logic should have prevented concurrent SB/DB RAM Access")
// Make copies of DB RAM data before writing.
val dbRamWrDataVec = Fill(1 << (dbRamAddrWidth - ramAddrWidth), dbRamWrData)
ramWrData := Mux(sbRamWrEn,
(ramWrMask & sbRamWrData ) | (~ramWrMask & ramRdData),
(ramWrMask & dbRamWrDataVec.toBits) | (~ramWrMask & ramRdData))
(ramWrMask & sbRamWrData ) | (~ramWrMask & ramRdData),
(ramWrMask & dbRamWrDataVec) | (~ramWrMask & ramRdData))
ramAddr := Mux(sbRamWrEn | sbRamRdEn, sbRamAddr,
dbRamAddr >> (dbRamAddrWidth - ramAddrWidth))
@ -700,7 +697,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
// haltnot handled in other logic
if (cfg.hasBusMaster){
// buserror is set 'until 0 is written to any bit in this field'.
CONTROLReg.buserror := Mux((CONTROLWrData.buserror === SInt(-1).toBits), CONTROLReg.buserror, UInt(0))
CONTROLReg.buserror := Mux(CONTROLWrData.buserror.andR, CONTROLReg.buserror, UInt(0))
CONTROLReg.autoincrement := CONTROLWrData.autoincrement
CONTROLReg.access := CONTROLWrData.access
}
@ -743,15 +740,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
dbRamRdEn := Bool(false)
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
dbRdData := RAMRdData.toBits()
dbRdData := RAMRdData.asUInt
dbRamRdEn := dbRdEn
}.elsewhen (dbReq.addr === DMCONTROL) {
dbRdData := CONTROLRdData.toBits()
dbRdData := CONTROLRdData.asUInt
}.elsewhen (dbReq.addr === DMINFO) {
dbRdData := DMINFORdData.toBits()
dbRdData := DMINFORdData.asUInt
}.elsewhen (dbReq.addr === HALTSUM) {
if (cfg.hasHaltSum){
dbRdData := HALTSUMRdData.toBits()
dbRdData := HALTSUMRdData.asUInt
} else {
dbRdData := UInt(0)
}

25
uncore/src/main/scala/devices/Dma.scala
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@ -5,6 +5,7 @@ import cde.{Parameters, Field}
import junctions._
import junctions.NastiConstants._
import uncore.tilelink._
import uncore.Util._
case object NDmaTransactors extends Field[Int]
case object NDmaXacts extends Field[Int]
@ -104,7 +105,7 @@ class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
val ctrl_regs = Reg(Vec(nCtrlWords, UInt(width = nastiXDataBits)))
val ctrl_idx = Reg(UInt(width = log2Up(nCtrlWords)))
val ctrl_done = Reg(Bool())
val ctrl_blob = ctrl_regs.toBits
val ctrl_blob = ctrl_regs.asUInt
val ctrl_id = Reg(UInt(width = nastiXIdBits))
val sizeOffset = 3 * addrBits
@ -228,7 +229,7 @@ class DmaTrackerFile(implicit p: Parameters) extends DmaModule()(p) {
}
val trackers = List.fill(nDmaTransactors) { Module(new DmaTracker) }
val reqReadys = Vec(trackers.map(_.io.dma.req.ready)).toBits
val reqReadys = trackers.map(_.io.dma.req.ready).asUInt
io.mem <> trackers.map(_.io.mem)
io.mmio <> trackers.map(_.io.mmio)
@ -305,10 +306,10 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
val (put_beat, put_done) = Counter(
io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
val put_mask = Vec.tabulate(tlDataBytes) { i =>
val put_mask = Seq.tabulate(tlDataBytes) { i =>
val byte_index = Cat(put_beat, UInt(i, tlByteAddrBits))
byte_index >= offset && byte_index < bytes_left
}.toBits
}.asUInt
val prefetch_sent = io.mem.acquire.fire() && io.mem.acquire.bits.isPrefetch()
val prefetch_busy = Reg(init = UInt(0, tlMaxClientXacts))
@ -324,14 +325,14 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
(value >> sel)(0)
when (alignment === UInt(0)) {
put_data := data_buffer.read(base_index)
put_data := data_buffer(base_index)
} .elsewhen (shift_dir) {
val shift_index = base_index - beat_align
when (bit_align === UInt(0)) {
put_data := data_buffer.read(shift_index)
put_data := data_buffer(shift_index)
} .otherwise {
val upper_bits = data_buffer.read(shift_index)
val lower_bits = data_buffer.read(shift_index - UInt(1))
val upper_bits = data_buffer(shift_index)
val lower_bits = data_buffer(shift_index - UInt(1))
val upper_shifted = upper_bits << bit_align
val lower_shifted = lower_bits >> rev_align
put_data := upper_shifted | lower_shifted
@ -339,10 +340,10 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
} .otherwise {
val shift_index = base_index + beat_align
when (bit_align === UInt(0)) {
put_data := data_buffer.read(shift_index)
put_data := data_buffer(shift_index)
} .otherwise {
val upper_bits = data_buffer.read(shift_index + UInt(1))
val lower_bits = data_buffer.read(shift_index)
val upper_bits = data_buffer(shift_index + UInt(1))
val lower_bits = data_buffer(shift_index)
val upper_shifted = upper_bits << rev_align
val lower_shifted = lower_bits >> bit_align
put_data := upper_shifted | lower_shifted
@ -502,7 +503,7 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
val write_half = gnt.client_xact_id(0)
val write_idx = Cat(write_half, gnt.addr_beat)
get_inflight := get_inflight & ~UIntToOH(write_idx)
data_buffer.write(write_idx, gnt.data)
data_buffer(write_idx) := gnt.data
} .otherwise {
put_inflight := Bool(false)
}

2
uncore/src/main/scala/devices/Plic.scala
View File

@ -154,7 +154,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
val word =
if (tlDataBytes >= pending.size) UInt(0)
else addr(log2Up(pending.size)-1,log2Up(tlDataBytes))
rdata := pending.toBits >> (word * tlDataBits)
rdata := pending.asUInt >> (word * tlDataBits)
}.otherwise {
val regsPerBeat = tlDataBytes >> log2Up(cfg.priorityBytes)
val word =

2
uncore/src/main/scala/tilelink/Arbiters.scala
View File

@ -144,7 +144,7 @@ trait AppendsArbiterId extends TileLinkArbiterLike {
else
UInt(0)
}
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0)
}
/** Uses the client_xact_id as is (assumes it has been set to port index) */

2
uncore/src/main/scala/tilelink/Definitions.scala
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@ -397,7 +397,7 @@ object Acquire {
Acquire.putPrefetchType -> Cat(M_XWR, alloc)))
}
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).toUInt
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).asUInt
// Most generic constructor
def apply(

4
uncore/src/main/scala/util/AmoAlu.scala
View File

@ -36,7 +36,7 @@ class StoreGenAligned(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) extends St
class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val t = new StoreGen(typ, addr, dat, maxSize)
private val signed = typ.toSInt >= SInt(0)
private val signed = typ.asSInt >= SInt(0)
private def genData(logMinSize: Int): UInt = {
var res = dat
@ -82,7 +82,7 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu
if (operandBits == 32) io.lhs + rhs
else {
val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
(io.lhs & mask).toUInt + (rhs & mask)
(io.lhs & mask) + (rhs & mask)
}
val less =