riscv/rocket-chip
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use isOneOf as much as possible

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This commit is contained in:
Howard Mao
2016-08-19 09:46:43 -07:00
parent d34e790ac0
commit 33676e81f8
9 changed files with 33 additions and 35 deletions
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2
uncore/src/main/scala/devices/Bram.scala
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@ -74,7 +74,7 @@ class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
(0 until max_size).map(sz => (UInt(sz) -> UInt((1 << (1 << sz)) - 1))))
val wmask = (wmask_lut << waddr(max_size - 1, 0))(hastiDataBytes - 1, 0)
val is_trans = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
val is_trans = io.hsel && io.htrans.isOneOf(HTRANS_NONSEQ, HTRANS_SEQ)
val raddr = io.haddr >> UInt(max_size)
val ren = is_trans && !io.hwrite
val bypass = Reg(init = Bool(false))

3
uncore/src/main/scala/devices/Debug.scala
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@ -4,6 +4,7 @@ package uncore.devices
import Chisel._
import uncore.tilelink._
import uncore.util._
import junctions._
import cde.{Parameters, Config, Field}
@ -901,7 +902,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
when (sbAddr(11, 8) === UInt(4)) { //0x400-0x4FF Debug RAM
sbRdData := sbRamRdData
sbRamRdEn := sbRdEn
}.elsewhen (sbAddr(11,8) === UInt(8) || sbAddr(11,8) === UInt(9)){ //0x800-0x9FF Debug ROM
}.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
if (cfg.hasDebugRom) {
sbRdData := sbRomRdData
} else {

13
uncore/src/main/scala/unittests/Drivers.scala
View File

@ -4,6 +4,7 @@ import Chisel._
import junctions._
import uncore.tilelink._
import uncore.constants._
import uncore.util._
import cde.Parameters
abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
@ -167,7 +168,7 @@ class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
val put_data = Fill(dataRep, put_cnt)(tlDataBits - 1, 0)
val get_data = Fill(dataRep, get_cnt)(tlDataBits - 1, 0)
io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
io.mem.acquire.bits := Mux(state === s_put_req,
Put(
client_xact_id = UInt(0),
@ -178,7 +179,7 @@ class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
client_xact_id = UInt(0),
addr_block = get_block,
addr_beat = get_beat))
io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
when (state === s_idle && io.start) { state := s_put_req }
when (state === s_put_req && io.mem.acquire.ready) { state := s_put_resp }
@ -239,7 +240,7 @@ class PutMaskDriver(minBytes: Int = 1)(implicit p: Parameters) extends Driver()(
}
io.finished := (state === s_done)
io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
io.mem.acquire.bits := Mux(state === s_put_req,
Put(
client_xact_id = UInt(0),
@ -251,7 +252,7 @@ class PutMaskDriver(minBytes: Int = 1)(implicit p: Parameters) extends Driver()(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_beat = UInt(0)))
io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
assert(!io.mem.grant.valid || state =/= s_get_resp ||
io.mem.grant.bits.data === expected,
@ -295,9 +296,9 @@ class PutBlockSweepDriver(val n: Int)(implicit p: Parameters)
addr_block = get_cnt)
io.finished := (state === s_done)
io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
io.mem.acquire.valid := state.isOneOf(s_put_req, s_get_req)
io.mem.acquire.bits := Mux(state === s_put_req, put_acquire, get_acquire)
io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
io.mem.grant.ready := state.isOneOf(s_put_resp, s_get_resp)
assert(!io.mem.grant.valid || state =/= s_get_resp ||
io.mem.grant.bits.data === get_data,