riscv/rocket-chip
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Remove parameters for some things that aren't parameterizable

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Heads up @colinschmidt and @ccelio.  I'm removing these because
they are ISA constants and so are not truly parameters, so the
parameter place is not the place for them.  Since BOOM and Hwacha
both depend on rocket, you should be able to obtain them by
instantiating/extending rocket.HasCoreParameters.
This commit is contained in:
Andrew Waterman
2016-08-16 20:04:02 -07:00
committed by Howard Mao
parent 33676e81f8
commit fee5d2b1ea
12 changed files with 22 additions and 43 deletions
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2
uncore/src/main/scala/agents/Cache.scala
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@ -664,7 +664,7 @@ trait HasAMOALU extends HasAcquireMetadataBuffer
// Provide a single ALU per tracker to merge Puts and AMOs with data being
// refilled, written back, or extant in the cache
val amoalu = Module(new AMOALU(rhsIsAligned = true))
val amoalu = Module(new AMOALU(amoAluOperandBits, rhsIsAligned = true))
val amo_result = Reg(init = UInt(0, innerDataBits))
def initializeAMOALUIOs() {

3
uncore/src/main/scala/converters/Ahb.scala
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@ -344,9 +344,8 @@ class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters)
// Execute Atomic ops; unused and optimized away if !supportAtomics
val amo_p = p.alterPartial({
case CacheBlockOffsetBits => hastiAddrBits
case AmoAluOperandBits => hastiDataBits
})
val alu = Module(new AMOALU(rhsIsAligned = true)(amo_p))
val alu = Module(new AMOALU(hastiDataBits, rhsIsAligned = true)(amo_p))
alu.io.addr := haddr
alu.io.cmd := cmd
alu.io.typ := hsize

2
uncore/src/main/scala/devices/Bram.scala
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@ -145,7 +145,7 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
data = Mux(r_acq.isAtomic(), r_old_data, ram(r_acq_addr)))
val amo_shift_bits = acq.amo_shift_bytes() << UInt(3)
val amoalu = Module(new AMOALU(rhsIsAligned = true))
val amoalu = Module(new AMOALU(amoAluOperandBits, rhsIsAligned = true))
amoalu.io.addr := Cat(acq.addr_block, acq.addr_beat, acq.addr_byte())
amoalu.io.cmd := acq.op_code()
amoalu.io.typ := acq.op_size()

6
uncore/src/main/scala/util/AmoAlu.scala
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@ -53,12 +53,10 @@ class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSiz
def data = genData(0)
}
class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Module {
val operandBits = p(AmoAluOperandBits)
val blockOffBits = p(CacheBlockOffsetBits)
class AMOALU(operandBits: Int, rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Module {
require(operandBits == 32 || operandBits == 64)
val io = new Bundle {
val addr = Bits(INPUT, blockOffBits)
val addr = Bits(INPUT, log2Ceil(operandBits/8))
val cmd = Bits(INPUT, M_SZ)
val typ = Bits(INPUT, log2Ceil(log2Ceil(operandBits/8) + 1))
val lhs = Bits(INPUT, operandBits)