Wesley W. Terpstra
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f99a3dbec7
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tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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5b31fb81fe
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tilelink2: IDNode needs to be specialized for output vs. input passthrough
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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eac4d44131
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tilelink2: don't apply HintHandler to B=>C by default
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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cc8112d02e
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tilelink2: pass E through the HintHandler
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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a72f7115ae
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tilelink2: optimize support testing circuits
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2016-09-05 20:58:39 -07:00 |
|
Wesley W. Terpstra
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f0cfd81820
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tilelink2: add an adapter to add support for Hints to devices
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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5f6ca0bd0d
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tilelink2: rename wmask => mask since it also applies to reads
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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7347b0c4dd
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tilelink2: TLLegacy converts from legacy TileLink to TileLink2
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2016-09-05 20:58:39 -07:00 |
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Wesley W. Terpstra
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fa472e38fb
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tilelink2: monitor error line legality
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2016-09-05 20:58:39 -07:00 |
|
Wesley W. Terpstra
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edb17d1e34
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tilelink2: document allowed (and required) response messages
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2016-09-05 20:58:38 -07:00 |
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Wesley W. Terpstra
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ec1f901a38
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tilelink2: move error from type into Bundle and add HintAck
We need Grant with errors too.
We also want to match response type to request type more easily.
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2016-09-05 20:58:38 -07:00 |
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Wesley W. Terpstra
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534d7f6eb6
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tilelink2: implement SRAM manager
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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32894a8e20
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tilelink2: transfers must never exceed 4kB
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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dd27a60daa
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tilelink2: use consistent in/out ports for TLSimpleFactories
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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1a87eef3e2
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tilelink2: add atomic message types
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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5f7711a0c0
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tilelink2: add an intermediate type for simple factories
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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967d8f108c
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tilelink2: support ready-valid enqueue+dequeue on register fields
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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77cf186cf0
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tilelink2: make bundle parameterization reusable
|
2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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594850eaae
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tilelink2: assert-fail on something more user understandable
|
2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
dc1164a996
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tilelink2: defer bundle construction until after Module base class instantiated
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
18e149098a
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tilelink2: connect abstract register-based modules to TileLink
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
917a9c8e5d
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tilelink2: forward declarations for message constructors
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
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4649c42f50
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tilelink2: use a new type in the signature of null-parameter Bundle methods
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
0ff33a31a4
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tilelink2: add a stub SRAM manager
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2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
a87c2d13e2
|
tilelink2: include an abstract definition for register mapped devices
|
2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
3a441d853f
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tilelink2: clarify that fifoId only applies to accesses (not hints)
|
2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
4b99bd3be1
|
tilelink2: mask out unnecessary address bits
|
2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
e24ba61754
|
tilelink2: distinguish two levels of uncacheability
|
2016-09-05 20:58:38 -07:00 |
|
Wesley W. Terpstra
|
e506309998
|
tilelink2: prototype crossbar implementation
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
34f65938b6
|
tilelink2: add a TLBundle constructor
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
1cd85ff050
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tilelink2: add some bundle introspection to scaffold the xbar
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
9c62f5d9c1
|
tilelink2: shave off a few more firrtl monitor lines
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
af29595979
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tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
d7e839280f
|
tilelink2: include legal message monitor
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
492a38aedc
|
tilelink2: only accesses can have errors (release must make forward progress)
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
6599bcb77b
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tilelink2: statically check Operations are remotely plausible
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
8cff45f254
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tilelink2: use byte-aligned addressing
This makes it possible to fully validate user input in a monitor.
We will override the lower bits with constant 0s in the TL connect.
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
45e152e97e
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tilelink2: include Operation constructors
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
5b10c1a328
|
tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3)
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
8592cbf0e3
|
tilelink2: Message and Permisison types from Henry
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
9a460322da
|
tilelink2: add synthesizable test methods for Parameters
|
2016-09-05 20:58:37 -07:00 |
|
Wesley W. Terpstra
|
7328b55abd
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tilelink2: first cut at parameterization
|
2016-09-05 20:58:37 -07:00 |
|
Howard Mao
|
59a2e6a4dc
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Merge pull request #244 from ucb-bar/compelete-dramsim-removal
remove remaining dramsim2 files
|
2016-09-05 15:05:38 -07:00 |
|
Colin Schmidt
|
ba4b3e14cc
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remove remaining dramsim2 files
|
2016-09-04 17:25:24 -07:00 |
|
Howard Mao
|
8906097250
|
have Travis cache the entire verilator directory
|
2016-09-04 15:05:30 -07:00 |
|
Howard Mao
|
a7f79aa409
|
get rid of TileLinkMemorySelector
|
2016-09-04 10:55:19 -07:00 |
|
Howard Mao
|
f0ab6d0214
|
tie off finish signals in tilelink wrapper and unwrapper
|
2016-09-04 10:55:19 -07:00 |
|
Howard Mao
|
66de89c4db
|
allow fixed priority routing in Junctions arbiters
|
2016-09-04 10:55:19 -07:00 |
|
Howard Mao
|
efe8670283
|
allow Serializer/Deserializer to work with arbitrary Chisel data types
|
2016-09-04 10:55:19 -07:00 |
|
Howard Mao
|
b9b79e4fb6
|
get rid of AtoS RTL
|
2016-09-04 10:55:19 -07:00 |
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