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3046 Commits

Author SHA1 Message Date
Howard Mao 0bd7ef1278 re-enable SCs inflight with other requests 2016-07-26 22:21:41 -07:00
Howard Mao df07771fa0 add uncached noise generator to TraceGen 2016-07-26 22:21:10 -07:00
Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86)
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
2016-07-26 18:41:52 -07:00
Howard Mao ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao 82bbbf908d Fix L2 Writeback deadlock issue
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
2016-07-26 12:31:08 -07:00
Howard Mao 1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao 6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Wesley W. Terpstra 11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter 2016-07-22 14:51:05 -07:00
Wesley W. Terpstra a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations 2016-07-22 14:48:22 -07:00
Howard Mao 51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Howard Mao 75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Howard Mao 9168f35971 clean up the requirements in StatelessBridge
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
2016-07-21 19:41:56 -07:00
Colin Schmidt a43ad522dc add clock override to tile constructor (#42)
useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
2016-07-21 17:56:52 -07:00
Howard Mao 12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Megan Wachs c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. 2016-07-21 13:54:28 -07:00
Megan Wachs eb9e998c08 Add ManagerToClientStatelessBridge 2016-07-21 13:49:16 -07:00
Howard Mao 0a1cd64786 fix number of builtin Acquire types 2016-07-21 13:45:20 -07:00
Howard Mao ffe17cbb2b bump uncore for L2 bugfix 2016-07-21 12:35:38 -07:00
Howard Mao 20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Howard Mao 86e31be820 fix lockup from back to back releases with data 2016-07-21 12:06:58 -07:00
Howard Mao 24ef4e6dea make sure to use AND not OR for combining finished signals 2016-07-21 12:05:11 -07:00
Howard Mao d77d0ddc5d rename CacheTest.scala to CacheFillTest.scala 2016-07-20 20:37:45 -07:00
Howard Mao d56362f04c add configuration checks for TraceGen 2016-07-20 10:37:10 -07:00
Howard Mao 959630630a give LCG an inc signal and add object constructors 2016-07-20 10:36:28 -07:00
Howard Mao b013925ab0 make sure ReleaseRegression starts only on io.start 2016-07-19 15:42:45 -07:00
Wesley W. Terpstra 9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00
Wesley W. Terpstra fa8317fec1 debug: add clock crossing primitives 2016-07-19 14:52:43 -07:00
Howard Mao 577c73667b use getSimpleName to dump out test names 2016-07-19 14:42:58 -07:00
Howard Mao 1dac2930eb fix bug in WriteMaskedPutBlockRegression 2016-07-19 14:42:23 -07:00
Howard Mao 19b44ec95b Bug fixes in SimpleHellaCacheIF and L2 agents
* SimpleHellaCacheIF now properly handles both the non-blocking data
   cache and blocking data cache.
 * SimpleHellaCacheIF maintains ordering of replayed requests
 * L2 VoluntaryReleaseTracker sends voluntary release grant properly
 * Coherence protocols now downgrade for probeCopy
2016-07-19 09:35:13 -07:00
Howard Mao bc39d52655 changes to multi-transaction timer 2016-07-18 18:26:18 -07:00
Henry Cook e406d1bd73 Make probeCopy have same behavior as probeDowngrade 2016-07-18 18:22:49 -07:00
Ben Keller c069e66056 Modify the RoCC interface to include status in the command queue. (#41)
This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.

This addresses the first half of #40.
2016-07-18 17:40:50 -07:00
Howard Mao 9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal 2016-07-18 17:38:20 -07:00
Howard Mao e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao 2723b2f515 fix issues in SimpleHellaCacheIF and document the changes 2016-07-18 17:02:47 -07:00
Howard Mao 40a146f625 HellaCacheArbiter passes through if n == 1 2016-07-18 17:01:29 -07:00
Howard Mao 39a1ecbf3c switch groundtest to merged master 2016-07-18 09:34:27 -07:00
Howard Mao 359252fdc1 fix a width bug 2016-07-18 09:33:17 -07:00
Howard Mao 6fc4236782 add atomic and prefetch drivers 2016-07-18 09:33:17 -07:00
Howard Mao 2ec736ed67 reorder some code in the Nasti unit tests 2016-07-18 09:33:17 -07:00
Howard Mao 3ea299b062 make unit test debug output more meaningful 2016-07-18 09:33:17 -07:00
Howard Mao def740406c fix a few Driver bugs 2016-07-18 09:33:17 -07:00
Howard Mao 8278a73e83 group unit tests by their tested interface 2016-07-18 09:33:17 -07:00
Howard Mao 9c0fffdd1c start constructing composable tilelink unit test drivers 2016-07-18 09:33:17 -07:00
Howard Mao c92732dcaa rename MemoryTestDriver to NastiDriver 2016-07-18 09:33:16 -07:00
Howard Mao c906e6edde some renaming 2016-07-18 09:33:16 -07:00
Howard Mao 1c2bf6e938 make list of unit tests a a parameter 2016-07-18 09:33:16 -07:00
Howard Mao 69eebaf362 factor out unit tests into separate package 2016-07-18 09:33:16 -07:00