Andrew Waterman
59ca373146
Merge pull request #18 from jackkoenig/master
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Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
2015-11-08 22:38:01 -08:00
jackkoenig
1e259a55da
Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
2015-11-08 21:16:31 -08:00
Yunsup Lee
df5daaa72e
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-06 23:57:42 -08:00
Andrew Waterman
2f515b2af6
Reduce critical path for fdiv valid signal
2015-11-06 23:28:31 -08:00
Colin Schmidt
86d67051b2
Merge commit 'e31be75' into rocc-fpu-port
2015-10-26 16:29:51 -07:00
Yunsup Lee
c7235fecb5
further state optimization in CSRfile when not UseVM
2015-10-25 10:23:46 -07:00
Colin Schmidt
652fb393a3
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-22 16:38:28 -07:00
Jim Lawson
0c587704a7
Add ability to generate libraryDependency on cde.
2015-10-22 11:37:20 -07:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Colin Schmidt
942f6a7d7f
Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port
2015-10-21 17:18:20 -07:00
Colin Schmidt
97f29b1618
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-21 11:33:42 -07:00
Howard Mao
0b7c828b5d
go back to using standard LockingArbiter
2015-10-21 09:15:51 -07:00
Howard Mao
c68d9f8137
make ProbeUnit state machine easier to understand
2015-10-20 23:25:23 -07:00
Henry Cook
1a1185be3f
Vectorize ROCC and Tile memory interfaces
2015-10-20 15:02:24 -07:00
Colin Schmidt
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
Henry Cook
6f8997bee9
Minor refactor of StoreGen/AMOALU.
2015-10-16 19:12:46 -07:00
Henry Cook
1441590c3b
add enabled field to BTBParameters
2015-10-16 19:12:39 -07:00
Henry Cook
969ecaecf8
pass parameters to BuildRoCC
2015-10-14 14:16:47 -07:00
Henry Cook
68cb54bc68
refactor tilelink params
2015-10-14 12:14:36 -07:00
Henry Cook
4508666d96
log2ceil
2015-10-06 18:22:47 -07:00
Henry Cook
8173695800
added HasAddrMapParameters
2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
Henry Cook
69a4dd0a79
refactor NASTI to not use param
2015-10-02 14:20:47 -07:00
Howard Mao
19656e4abe
make sure to generate release from clean coh state on probe miss
2015-09-30 16:58:18 -07:00
Andrew Waterman
833909a2b5
Chisel3 compatibility fixes
2015-09-30 14:36:26 -07:00
Andrew Waterman
a7c908cb83
Don't declare Reg inside of when
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We haven't yet decided what the Chisel3 semantics for this will be.
2015-09-30 12:43:36 -07:00
Howard Mao
2f3d15675c
fix DataArray writemask in L1D
2015-09-28 16:02:39 -07:00
Andrew Waterman
f8a7a80644
Make perf counters optional
2015-09-28 13:55:23 -07:00
Andrew Waterman
5e88ead984
Add pseudo-ops to instructions.scala
2015-09-28 11:52:27 -07:00
Andrew Waterman
b93a94597c
Remove needless control logic
2015-09-27 13:31:52 -07:00
Howard Mao
4bda6b6757
fix bug in tlb refill
2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef
make sure passthrough requests are treated as vm_enabled = false
2015-09-26 20:29:51 -07:00
Andrew Waterman
c3fff12ff0
Revert "replace remaining uses of Vec.fill"
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This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
2015-09-25 17:09:06 -07:00
Andrew Waterman
0bfb2962a6
Assume coh.isRead returns true for store-conditional
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This requires an uncore update.
2015-09-25 15:26:11 -07:00
Howard Mao
a66bdb1956
replace remaining uses of Vec.fill
2015-09-24 17:53:26 -07:00
Howard Mao
9eb988a4c6
make sure access to invalid physical address treated as exception
2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a
don't mux data_word_bypass between IOMSHR and cache
2015-09-22 10:10:57 -07:00
Howard Mao
d89bcd3922
modify csr file to bring in line with HTIF changes
2015-09-22 10:10:57 -07:00
Howard Mao
382faba4a6
Implement bypassing L1 data cache for MMIO
2015-09-22 10:10:57 -07:00
Andrew Waterman
e72e5a34b5
Fix storage of SP values in DP registers
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The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s. This meant that an FSD + FLD of that register
would not restore the value properly.
Also, minor code cleanup.
2015-09-21 12:20:44 -07:00
Christopher Celio
76bf1da310
[commitlog] zero-extend SP write-back values
2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c
[commitlog] don't print out writebacks to x0
2015-09-15 16:47:26 -07:00
Christopher Celio
e22bf02a80
[commitlog] CSR's cycle optionally set to instret
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- Allows debugging Rocket against Spike by having timer interrupts
occur in the same place in the instruction stream for both.
2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262
[commitlog] Added privilege-level to output
2015-09-15 16:47:24 -07:00
Christopher Celio
53a02a62c8
[commitlog] Fix sp/dp bug in FPU writeback
2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857
[commitlog] Added FP instructions to the commitlog
2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c
[commitlog] Initial commit log for integer working
2015-09-15 15:59:03 -07:00
Andrew Waterman
78b2e947de
Chisel3 compatibility fixes
2015-09-11 15:43:07 -07:00
Colin Schmidt
d292b6cb13
don't connect rocc-fpu-port without rocc accel
2015-09-08 14:44:12 -07:00
Albert Ou
3d6a060dc3
Bump Scala to 2.11.6
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This change, originally part of commit b978083, was excluded from the
merge at commit 47494ec.
2015-08-10 23:52:58 -07:00
