Henry Cook
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866396545d
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For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten
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2015-07-23 17:00:22 -07:00 |
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Yunsup Lee
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caf89baeb7
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update zscale
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2015-07-23 13:59:45 -07:00 |
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Henry Cook
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bd4ff35a4b
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Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
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2015-07-22 11:49:10 -07:00 |
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Yunsup Lee
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d6df479870
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move 'include /Makefrag' out of top-level Makefrag
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2015-07-14 16:13:32 -07:00 |
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Henry Cook
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407d8e473e
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first cut at parameter-based testing
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2015-07-13 14:54:26 -07:00 |
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Yunsup Lee
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09e29e8fe0
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add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
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2015-07-07 20:38:47 -07:00 |
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Yunsup Lee
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e6a13cdeba
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New machine-mode timer facility
Mirroring Andrew's commit to reference-chip
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2015-07-07 17:26:07 -07:00 |
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Henry Cook
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854fd64fba
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Added optional Makefile includes for private chip repos
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2015-07-06 17:15:27 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Yunsup Lee
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7a28d2b47c
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forgot to move more hwacha stuff out in rocket-chip
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2014-09-25 15:34:18 -07:00 |
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Yunsup Lee
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275b72368b
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add CONFIG to the name of simulator executable
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2014-09-11 22:11:58 -07:00 |
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Yunsup Lee
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086bb02c24
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check RISCV envirnoment variable
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2014-09-11 02:38:21 -07:00 |
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Yunsup Lee
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02c08a156f
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generate consts.vh from chisel source
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2014-09-10 17:14:55 -07:00 |
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Yunsup Lee
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cfecd8832d
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tease out reference-chip specific stuff
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2014-09-09 20:49:28 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
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Henry Cook
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82467313dd
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merge in rocketchip changes from master
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2014-09-02 13:51:57 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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Adam Izraelevitz
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fcd68364ff
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Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
src/main/scala/ReferenceChip.scala
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2014-08-01 18:07:22 -07:00 |
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Henry Cook
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1bf5439f0b
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include new mm test in benchmarks
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2014-04-18 18:05:30 -07:00 |
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Andrew Waterman
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f04bde75fb
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New FP encoding
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2014-03-11 19:12:20 -07:00 |
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Yunsup Lee
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23045ec379
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add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv
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2014-03-02 03:38:06 -08:00 |
|
Yunsup Lee
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bcfcdefe88
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update hwacha
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2014-02-27 04:39:12 -08:00 |
|
Yunsup Lee
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46714c0c60
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more improvements to hwacha
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2014-02-26 21:20:53 -08:00 |
|
Yunsup Lee
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a5625de3d5
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support vector irq tests
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2014-02-25 21:18:03 -08:00 |
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Yunsup Lee
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e5c2bd5e7b
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add extensions option to riscv-dis for better disassembly
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2014-02-25 03:50:32 -08:00 |
|
Adam Izraelevitz
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58d2e62e3f
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Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
chisel
src/main/scala/ReferenceChip.scala
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2014-02-19 14:24:36 -08:00 |
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Stephen Twigg
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6808245bb5
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Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging.
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2014-02-12 16:50:13 -08:00 |
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Adam Izraelevitz
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548cf16061
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Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse
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2014-02-11 14:36:47 -08:00 |
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Yunsup Lee
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dbeadba2dc
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add vfmvv
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2014-02-05 03:28:33 -08:00 |
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Stephen Twigg
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8c96e27ca6
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Merge branch 'master' into hwacha-port
Mostly Stable version that is passing tests
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2014-02-04 17:20:28 -08:00 |
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Andrew Waterman
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e9d3a650a4
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Speed up C++ compilation
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2014-01-31 12:25:19 -08:00 |
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Andrew Waterman
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b6c6bddb62
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Add full CSRRx support and an asm test
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2014-01-21 16:20:24 -08:00 |
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Yunsup Lee
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5642194834
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push hwacha to consistent state
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2013-11-20 16:44:33 -08:00 |
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Stephen Twigg
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a870f51300
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Add some vector tests
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2013-11-14 15:56:25 -08:00 |
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Andrew Waterman
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628745226c
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Use spike disassembler riscv-dis if it exists
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2013-09-15 04:25:53 -07:00 |
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Andrew Waterman
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fbdbb01232
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update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
|
Henry Cook
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896179cbb6
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removed bad mt test
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2013-06-14 00:14:18 -07:00 |
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Henry Cook
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85fbb650c9
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makefile support for new multithreading tests
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2013-06-13 15:34:54 -07:00 |
|
Yunsup Lee
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a86ad08c1e
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commit awesome vlsi/energy scripts
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2013-05-01 02:59:11 -07:00 |
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Yunsup Lee
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a2f584e928
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add riscv-tests, get rid of riscv-asmtests-bmarks
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2013-04-29 19:29:51 -07:00 |
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Yunsup Lee
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9114012def
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assmebly tests are now built from riscv-tests
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2013-04-24 01:59:14 -07:00 |
|
Andrew Waterman
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7f5282d355
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replace RDNPC with AUIPC
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2013-04-22 04:21:46 -07:00 |
|
Andrew Waterman
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7ea782fd22
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add LR/SC
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2013-04-07 19:36:15 -07:00 |
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Andrew Waterman
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ef4927c9ad
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use a named pipe for VCD -> VPD conversion
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2013-03-25 16:19:19 -07:00 |
|
Yunsup Lee
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bc140ce9bc
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add vec_{vvadd,cmplxmult,matmul} bmarks
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2013-03-19 00:43:51 -07:00 |
|
Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
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2012-12-04 07:04:26 -08:00 |
|
Andrew Waterman
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7330deb13a
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print stack trace if elaboration fails
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2012-11-20 05:39:48 -08:00 |
|
Andrew Waterman
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4ed2d614a2
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update to new rocket; retime fpu in dc-syn
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2012-11-04 16:43:02 -08:00 |
|
Andrew Waterman
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367b5489d1
|
first crack at continuous compilation/testing flow
try it out: cd emulator; make test
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2012-10-19 04:09:07 -07:00 |
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