514 lines
11 KiB
Plaintext
514 lines
11 KiB
Plaintext
# Makefile snippet used by emulator/vlsi/fpga backends
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MODEL := Top
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CXX := g++
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CXXFLAGS := -O2 -g
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SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
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DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard $(basedir)/dramsim2/*.cpp))
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$(DRAMSIM_OBJS): %.o: %.cpp
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$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
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libdramsim.a: $(DRAMSIM_OBJS)
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ar rcs $@ $^
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#--------------------------------------------------------------------
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# Tests
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#--------------------------------------------------------------------
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# Globally installed assembly tests
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global_tstdir = $(basedir)/riscv-asmtests-bmarks/riscv-tests
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global_asm_tests = \
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riscv_ipi \
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riscv_add \
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riscv_addi \
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riscv_amoadd_d \
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riscv_amoadd_w \
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riscv_amoand_d \
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riscv_amoand_w \
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riscv_amoor_d \
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riscv_amoor_w \
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riscv_amoswap_d \
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riscv_amoswap_w \
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riscv_amomax_d \
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riscv_amomax_w \
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riscv_amomaxu_d \
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riscv_amomaxu_w \
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riscv_amomin_d \
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riscv_amomin_w \
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riscv_amominu_d \
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riscv_amominu_w \
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riscv_fence_i \
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riscv_sb \
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riscv_sd \
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riscv_sh \
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riscv_sw \
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riscv_addiw \
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riscv_addw \
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riscv_and \
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riscv_andi \
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riscv_beq \
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riscv_bge \
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riscv_bgeu \
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riscv_blt \
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riscv_bltu \
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riscv_bne \
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riscv_div \
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riscv_divu \
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riscv_divuw \
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riscv_divw \
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riscv_j \
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riscv_jal \
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riscv_jalr \
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riscv_jalr_j \
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riscv_jalr_r \
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riscv_lb \
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riscv_lbu \
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riscv_ld \
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riscv_lh \
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riscv_lhu \
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riscv_lui \
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riscv_lw \
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riscv_lwu \
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riscv_mul \
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riscv_mulh \
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riscv_mulhsu \
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riscv_mulhu \
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riscv_mulw \
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riscv_or \
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riscv_ori \
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riscv_rdnpc \
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riscv_rem \
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riscv_remu \
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riscv_remuw \
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riscv_remw \
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riscv_simple \
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riscv_sll \
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riscv_slli \
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riscv_slliw \
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riscv_sllw \
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riscv_slt \
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riscv_slti \
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riscv_sltiu \
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riscv_sltu \
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riscv_sra \
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riscv_srai \
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riscv_sraiw \
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riscv_sraw \
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riscv_srliw \
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riscv_srlw \
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riscv_sub \
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riscv_subw \
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riscv_xor \
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riscv_xori \
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riscv_fp_ldst \
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riscv_fp_move \
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riscv_fsgnj \
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riscv_fcmp \
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riscv_fcvt \
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riscv_fcvt_w \
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riscv_fadd \
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riscv_fmin \
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riscv_fmadd \
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riscv_fp_structural \
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global_asm_vm_tests = \
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riscv_add_vm \
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riscv_addi_vm \
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riscv_amoadd_d_vm \
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riscv_amoadd_w_vm \
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riscv_amoand_d_vm \
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riscv_amoand_w_vm \
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riscv_amoor_d_vm \
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riscv_amoor_w_vm \
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riscv_amoswap_d_vm \
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riscv_amoswap_w_vm \
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riscv_amomax_d_vm \
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riscv_amomax_w_vm \
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riscv_amomaxu_d_vm \
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riscv_amomaxu_w_vm \
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riscv_amomin_d_vm \
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riscv_amomin_w_vm \
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riscv_amominu_d_vm \
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riscv_amominu_w_vm \
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riscv_fence_i_vm \
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riscv_sb_vm \
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riscv_sd_vm \
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riscv_sh_vm \
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riscv_sw_vm \
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riscv_addiw_vm \
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riscv_addw_vm \
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riscv_and_vm \
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riscv_andi_vm \
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riscv_beq_vm \
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riscv_bge_vm \
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riscv_bgeu_vm \
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riscv_blt_vm \
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riscv_bltu_vm \
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riscv_bne_vm \
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riscv_div_vm \
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riscv_divu_vm \
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riscv_divuw_vm \
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riscv_divw_vm \
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riscv_j_vm \
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riscv_jal_vm \
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riscv_jalr_vm \
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riscv_jalr_j_vm \
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riscv_jalr_r_vm \
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riscv_lb_vm \
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riscv_lbu_vm \
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riscv_ld_vm \
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riscv_lh_vm \
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riscv_lhu_vm \
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riscv_lui_vm \
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riscv_lw_vm \
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riscv_lwu_vm \
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riscv_mul_vm \
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riscv_mulh_vm \
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riscv_mulhsu_vm \
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riscv_mulhu_vm \
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riscv_mulw_vm \
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riscv_or_vm \
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riscv_ori_vm \
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riscv_rdnpc_vm \
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riscv_rem_vm \
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riscv_remu_vm \
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riscv_remuw_vm \
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riscv_remw_vm \
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riscv_sll_vm \
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riscv_slli_vm \
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riscv_slliw_vm \
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riscv_sllw_vm \
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riscv_slt_vm \
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riscv_slti_vm \
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riscv_sltiu_vm \
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riscv_sltu_vm \
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riscv_sra_vm \
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riscv_srai_vm \
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riscv_sraiw_vm \
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riscv_sraw_vm \
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riscv_srliw_vm \
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riscv_srlw_vm \
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riscv_sub_vm \
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riscv_subw_vm \
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riscv_xor_vm \
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riscv_xori_vm \
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riscv_fp_ldst_vm \
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riscv_fp_move_vm \
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riscv_fsgnj_vm \
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riscv_fcmp_vm \
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riscv_fcvt_vm \
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riscv_fcvt_w_vm \
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riscv_fadd_vm \
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riscv_fmin_vm \
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riscv_fmadd_vm \
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riscv_fp_structural_vm \
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global_vecasm_tests = \
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riscv_vec_wakeup_vec \
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riscv_vec_fence_vec \
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riscv_vec_utidx_vec \
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riscv_vec_vmsv_vec \
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riscv_vec_vmvv_vec \
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riscv_vec_vfmvv_vec \
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riscv_vec_movz_vec \
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riscv_vec_movn_vec \
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riscv_vec_fmovz_vec \
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riscv_vec_fmovn_vec \
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riscv_vec_ld_vec \
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riscv_vec_lw_vec \
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riscv_vec_lwu_vec \
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riscv_vec_lh_vec \
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riscv_vec_lhu_vec \
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riscv_vec_lb_vec \
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riscv_vec_lbu_vec \
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riscv_vec_sd_vec \
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riscv_vec_sw_vec \
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riscv_vec_sh_vec \
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riscv_vec_sb_vec \
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riscv_vec_fld_vec \
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riscv_vec_flw_vec \
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riscv_vec_fsd_vec \
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riscv_vec_fsw_vec \
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riscv_vec_fcvt-d-l_vec \
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riscv_vec_vvadd_d_vec \
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riscv_vec_vvadd_fw_vec \
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riscv_vec_vvadd_fd_vec \
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riscv_vec_vvadd_w_vec \
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riscv_vec_vvmul_d_vec \
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riscv_vec_amoadd_d_vec \
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riscv_vec_amoswap_d_vec \
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riscv_vec_amoand_d_vec \
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riscv_vec_amoor_d_vec \
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riscv_vec_amomax_d_vec \
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riscv_vec_amomin_d_vec \
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riscv_vec_amomaxu_d_vec \
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riscv_vec_amominu_d_vec \
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riscv_vec_amoadd_w_vec \
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riscv_vec_amoswap_w_vec \
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riscv_vec_amoand_w_vec \
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riscv_vec_amoor_w_vec \
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riscv_vec_amomax_w_vec \
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riscv_vec_amomin_w_vec \
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riscv_vec_amomaxu_w_vec \
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riscv_vec_amominu_w_vec \
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riscv_vec_imul_vec \
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riscv_vec_fma_vec \
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riscv_mul_vec \
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riscv_mulw_vec \
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riscv_mulh_vec \
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riscv_mulhu_vec \
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riscv_mulhsu_vec \
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riscv_addi_vec \
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riscv_add_vec \
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riscv_addiw_vec \
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riscv_addw_vec \
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riscv_and_vec \
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riscv_andi_vec \
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riscv_lui_vec \
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riscv_or_vec \
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riscv_ori_vec \
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riscv_slt_vec \
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riscv_sltu_vec \
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riscv_slti_vec \
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riscv_sltiu_vec \
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riscv_slli_vec \
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riscv_sll_vec \
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riscv_slliw_vec \
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riscv_sllw_vec \
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riscv_srai_vec \
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riscv_sra_vec \
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riscv_sraiw_vec \
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riscv_sraw_vec \
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riscv_srli_vec \
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riscv_srl_vec \
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riscv_srliw_vec \
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riscv_srlw_vec \
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riscv_sub_vec \
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riscv_subw_vec \
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riscv_xor_vec \
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riscv_xori_vec \
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riscv_fadd_vec \
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riscv_fsgnj_vec \
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riscv_fmin_vec \
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riscv_fmadd_vec \
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riscv_fcvt_w_vec \
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riscv_fcvt_vec \
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riscv_fcmp_vec \
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riscv_vec_xcpt_ma_inst \
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riscv_vec_xcpt_illegal \
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riscv_vec_xcpt_illegal_vt_regid \
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riscv_vec_xcpt_illegal_tvec_regid \
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riscv_vec_ma_vld \
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riscv_vec_ma_vsd \
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riscv_vec_ma_utld \
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riscv_vec_ma_utsd \
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riscv_vec_illegal_tvec \
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global_vecasm_vm_tests = \
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riscv_vec_wakeup_vec_vm \
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riscv_vec_fence_vec_vm \
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riscv_vec_utidx_vec_vm \
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riscv_vec_vmsv_vec_vm \
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riscv_vec_vmvv_vec_vm \
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riscv_vec_vfmvv_vec_vm \
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riscv_vec_movz_vec_vm \
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riscv_vec_movn_vec_vm \
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riscv_vec_fmovz_vec_vm \
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riscv_vec_fmovn_vec_vm \
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riscv_vec_ld_vec_vm \
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riscv_vec_lw_vec_vm \
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riscv_vec_lwu_vec_vm \
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riscv_vec_lh_vec_vm \
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riscv_vec_lhu_vec_vm \
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riscv_vec_lb_vec_vm \
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riscv_vec_lbu_vec_vm \
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riscv_vec_sd_vec_vm \
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riscv_vec_sw_vec_vm \
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riscv_vec_sh_vec_vm \
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riscv_vec_sb_vec_vm \
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riscv_vec_fld_vec_vm \
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riscv_vec_flw_vec_vm \
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riscv_vec_fsd_vec_vm \
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riscv_vec_fsw_vec_vm \
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riscv_vec_fcvt-d-l_vec_vm \
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riscv_vec_vvadd_d_vec_vm \
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riscv_vec_vvadd_fw_vec_vm \
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riscv_vec_vvadd_fd_vec_vm \
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riscv_vec_vvadd_w_vec_vm \
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riscv_vec_vvmul_d_vec_vm \
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riscv_vec_amoadd_d_vec_vm \
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riscv_vec_amoswap_d_vec_vm \
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riscv_vec_amoand_d_vec_vm \
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riscv_vec_amoor_d_vec_vm \
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riscv_vec_amomax_d_vec_vm \
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riscv_vec_amomin_d_vec_vm \
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riscv_vec_amomaxu_d_vec_vm \
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riscv_vec_amominu_d_vec_vm \
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riscv_vec_amoadd_w_vec_vm \
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riscv_vec_amoswap_w_vec_vm \
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riscv_vec_amoand_w_vec_vm \
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riscv_vec_amoor_w_vec_vm \
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riscv_vec_amomax_w_vec_vm \
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riscv_vec_amomin_w_vec_vm \
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riscv_vec_amomaxu_w_vec_vm \
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riscv_vec_amominu_w_vec_vm \
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riscv_vec_imul_vec_vm \
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riscv_vec_fma_vec_vm \
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riscv_mul_vec_vm \
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riscv_mulw_vec_vm \
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riscv_mulh_vec_vm \
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riscv_mulhu_vec_vm \
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riscv_mulhsu_vec_vm \
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riscv_addi_vec_vm \
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riscv_add_vec_vm \
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riscv_addiw_vec_vm \
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riscv_addw_vec_vm \
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riscv_and_vec_vm \
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riscv_andi_vec_vm \
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riscv_lui_vec_vm \
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riscv_or_vec_vm \
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riscv_ori_vec_vm \
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riscv_slt_vec_vm \
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riscv_sltu_vec_vm \
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riscv_slti_vec_vm \
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riscv_sltiu_vec_vm \
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riscv_slli_vec_vm \
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riscv_sll_vec_vm \
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riscv_slliw_vec_vm \
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riscv_sllw_vec_vm \
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riscv_srai_vec_vm \
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riscv_sra_vec_vm \
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riscv_sraiw_vec_vm \
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riscv_sraw_vec_vm \
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riscv_srli_vec_vm \
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riscv_srl_vec_vm \
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riscv_srliw_vec_vm \
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riscv_srlw_vec_vm \
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riscv_sub_vec_vm \
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riscv_subw_vec_vm \
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riscv_xor_vec_vm \
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riscv_xori_vec_vm \
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riscv_fadd_vec_vm \
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riscv_fsgnj_vec_vm \
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riscv_fmin_vec_vm \
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riscv_fmadd_vec_vm \
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riscv_fcvt_w_vec_vm \
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riscv_fcvt_vec_vm \
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riscv_fcmp_vec_vm \
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global_vecasm_timer_tests = \
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riscv_vec_wakeup_vec_timer \
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riscv_vec_fence_vec_timer \
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riscv_vec_vvadd_d_vec_timer \
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riscv_vec_vvadd_fw_vec_timer \
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riscv_vec_vvadd_fd_vec_timer \
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riscv_vec_vvadd_w_vec_timer \
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riscv_vec_vvmul_d_vec_timer \
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riscv_vec_fcvt-d-l_vec_timer \
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riscv_vec_utidx_vec_timer \
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riscv_vec_vmvv_vec_timer \
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riscv_vec_vmsv_vec_timer \
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riscv_vec_vfmvv_vec_timer \
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riscv_vec_movz_vec_timer \
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riscv_vec_movn_vec_timer \
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riscv_vec_fmovz_vec_timer \
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riscv_vec_fmovn_vec_timer \
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riscv_vec_ld_vec_timer \
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riscv_vec_lw_vec_timer \
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riscv_vec_lwu_vec_timer \
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riscv_vec_lh_vec_timer \
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riscv_vec_lhu_vec_timer \
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riscv_vec_lb_vec_timer \
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riscv_vec_lbu_vec_timer \
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riscv_vec_sd_vec_timer \
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riscv_vec_sw_vec_timer \
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riscv_vec_sh_vec_timer \
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riscv_vec_sb_vec_timer \
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riscv_vec_fld_vec_timer \
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riscv_vec_flw_vec_timer \
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riscv_vec_fsd_vec_timer \
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riscv_vec_fsw_vec_timer \
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riscv_vec_amoadd_d_vec_timer \
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riscv_vec_amoswap_d_vec_timer \
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riscv_vec_amoand_d_vec_timer \
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riscv_vec_amoor_d_vec_timer \
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riscv_vec_amomax_d_vec_timer \
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riscv_vec_amomin_d_vec_timer \
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riscv_vec_amomaxu_d_vec_timer \
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riscv_vec_amominu_d_vec_timer \
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riscv_vec_amoadd_w_vec_timer \
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riscv_vec_amoswap_w_vec_timer \
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riscv_vec_amoand_w_vec_timer \
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riscv_vec_amoor_w_vec_timer \
|
|
riscv_vec_amomax_w_vec_timer \
|
|
riscv_vec_amomin_w_vec_timer \
|
|
riscv_vec_amomaxu_w_vec_timer \
|
|
riscv_vec_amominu_w_vec_timer \
|
|
riscv_vec_imul_vec_timer \
|
|
riscv_vec_fma_vec_timer \
|
|
riscv_mul_vec_timer \
|
|
riscv_mulw_vec_timer \
|
|
riscv_mulh_vec_timer \
|
|
riscv_mulhu_vec_timer \
|
|
riscv_mulhsu_vec_timer \
|
|
riscv_addi_vec_timer \
|
|
riscv_add_vec_timer \
|
|
riscv_addiw_vec_timer \
|
|
riscv_addw_vec_timer \
|
|
riscv_and_vec_timer \
|
|
riscv_andi_vec_timer \
|
|
riscv_lui_vec_timer \
|
|
riscv_or_vec_timer \
|
|
riscv_ori_vec_timer \
|
|
riscv_slt_vec_timer \
|
|
riscv_sltu_vec_timer \
|
|
riscv_slti_vec_timer \
|
|
riscv_sltiu_vec_timer \
|
|
riscv_slli_vec_timer \
|
|
riscv_sll_vec_timer \
|
|
riscv_slliw_vec_timer \
|
|
riscv_sllw_vec_timer \
|
|
riscv_srai_vec_timer \
|
|
riscv_sra_vec_timer \
|
|
riscv_sraiw_vec_timer \
|
|
riscv_sraw_vec_timer \
|
|
riscv_srli_vec_timer \
|
|
riscv_srl_vec_timer \
|
|
riscv_srliw_vec_timer \
|
|
riscv_srlw_vec_timer \
|
|
riscv_sub_vec_timer \
|
|
riscv_subw_vec_timer \
|
|
riscv_xor_vec_timer \
|
|
riscv_xori_vec_timer \
|
|
riscv_fadd_vec_timer \
|
|
riscv_fsgnj_vec_timer \
|
|
riscv_fmin_vec_timer \
|
|
riscv_fmadd_vec_timer \
|
|
riscv_fcvt_w_vec_timer \
|
|
riscv_fcvt_vec_timer \
|
|
riscv_fcmp_vec_timer \
|
|
|
|
# Globally installed benchmarks
|
|
|
|
global_bmarkdir = $(basedir)/riscv-asmtests-bmarks/riscv-bmarks
|
|
global_bmarks = \
|
|
median.riscv \
|
|
multiply.riscv \
|
|
qsort.riscv \
|
|
towers.riscv \
|
|
vvadd.riscv \
|
|
dgemm.riscv \
|
|
dhrystone.riscv \
|
|
spmv.riscv \
|
|
vec_vvadd.riscv \
|
|
vec_cmplxmult.riscv \
|
|
vec_matmul.riscv \
|
|
|
|
global_vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
|
|
global_vec_bmarks = \
|
|
ubmark-vvadd \
|
|
ubmark-bin-search \
|
|
ubmark-cmplx-mult \
|
|
ubmark-masked-filter \
|