riscv/rocket-chip
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generate consts.vh from chisel source

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This commit is contained in:
Yunsup Lee
2014-09-10 17:14:55 -07:00
parent cfecd8832d
commit 02c08a156f
8 changed files with 23 additions and 27 deletions
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9
Makefrag
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@ -22,14 +22,19 @@ timeout_cycles = 100000000
# Verilog Generation
#--------------------------------------------------------------------
# VLSI Backend
$(generated_dir)/$(MODEL).v: $(chisel_srcs)
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG)"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG) --configDump"
cd $(generated_dir) && \
if [ -a $(MODEL).conf ]; then \
$(mem_gen) $(generated_dir)/$(MODEL).conf >> $(generated_dir)/$(MODEL).v; \
fi
$(generated_dir)/consts.vh: $(generated_dir)/rocketchip.$(CONFIG).prm
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
echo "\`endif // CONST_VH" >> $@
$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"