riscv/rocket-chip
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Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse

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This commit is contained in:
Adam Izraelevitz
2014-02-11 14:36:47 -08:00
parent 7c11cf49b8
commit 548cf16061
4 changed files with 12 additions and 4 deletions
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Makefrag
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@ -14,6 +14,11 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
src_path = src/main/scala
#DESIGN := design_dsize8_c20b273
SRC := rocket/$(src_path)/*.scala hwacha/$(src_path)/*.scala /uncore/$(src_path)/*.scala $(src_path)/*.scala
PROJ := referencechip
#--------------------------------------------------------------------
# Tests
#--------------------------------------------------------------------