riscv/rocket-chip
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add zscale

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only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
This commit is contained in:
Yunsup Lee
2015-07-07 20:38:47 -07:00
parent e6a13cdeba
commit 09e29e8fe0
5 changed files with 79 additions and 5 deletions
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Makefrag
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@ -30,7 +30,7 @@ timeout_cycles = 100000000
#--------------------------------------------------------------------
$(generated_dir)/$(MODEL).$(CONFIG).v: $(chisel_srcs)
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --W0W --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)"
cd $(generated_dir) && \
if [ -a $(MODEL).$(CONFIG).conf ]; then \
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \
@ -43,7 +43,7 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
echo "\`endif // CONST_VH" >> $@
$(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
#--------------------------------------------------------------------
# DRAMSim2