 Howard Mao
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5abfd1a4ab
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make sure to check for region violations in DMA frontend
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2016-02-03 15:40:44 -08:00 |
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Howard Mao
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78579672d3
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make mtvec configurable and writeable
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2016-01-29 14:51:56 -08:00 |
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Howard Mao
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7937fbf074
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fix number of IOMSHRs at 1
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2016-01-29 14:51:56 -08:00 |
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Howard Mao
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305185c034
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send DMA requests through MMIO and get responses through CSRs
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2016-01-29 14:51:56 -08:00 |
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Howard Mao
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d170fcd913
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DecoupledHelper is now imported from junctions
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2016-01-21 15:38:43 -08:00 |
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Howard Mao
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77e068c153
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fix Chisel3 compat issue in SimpleHellaCacheIF
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2016-01-14 22:42:44 -08:00 |
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Howard Mao
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120361226d
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fix more Chisel3 deprecations
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2016-01-14 14:46:31 -08:00 |
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Howard Mao
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d51c127646
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fix deprecation warnings in rocket.scala
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2016-01-13 22:08:06 -08:00 |
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Howard Mao
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13ce91e453
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fix Chisel3 compat warnings in ICache and FPU
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2016-01-12 12:43:48 -08:00 |
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Howard Mao
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05b359d357
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support streaming DMA in DMA frontend
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2016-01-06 18:17:41 -08:00 |
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Howard Mao
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dbe68056d9
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Merge pull request #21 from ucb-bar/dma
Implement client-side DMA controller
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2015-12-22 10:33:28 -05:00 |
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Howard Mao
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304d8b814a
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Implement client-side DMA controller
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2015-12-16 21:24:24 -08:00 |
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Howard Mao
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7690de07e1
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allow icache to configure which side of the way mux gets buffered
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2015-12-02 17:17:49 -08:00 |
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Howard Mao
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369ee74a2c
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change names of RoCC tilelink interfaces to be more sensible
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2015-12-02 16:28:23 -08:00 |
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Howard Mao
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f67b02fadb
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Merge branch 'rocc-fpu-port'
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2015-12-02 08:52:15 -08:00 |
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Howard Mao
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73b0263663
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disconnect fpu port if no fpu-using RoCC accelerators
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2015-12-01 20:41:58 -08:00 |
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Howard Mao
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3f8f726296
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make rocc build independent from parameter structure
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2015-12-01 18:47:52 -08:00 |
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Howard Mao
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dcca0b1d86
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fix up FPU connection
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2015-12-01 18:14:58 -08:00 |
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Howard Mao
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08f77ca90d
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Merge branch 'master' into rocc-fpu-port
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2015-12-01 18:00:28 -08:00 |
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Howard Mao
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e76dfa55f7
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change the way rocc is parameterized
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2015-12-01 17:54:56 -08:00 |
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Howard Mao
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4833d41dbc
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make the connection of FPU ports optional per accelerator
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2015-12-01 16:48:05 -08:00 |
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Howard Mao
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0b15b19381
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add arbiter for FPU
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2015-12-01 10:22:31 -08:00 |
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Howard Mao
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1db2da00f3
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Merge branch 'master' into rocc-fpu-port
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2015-11-30 19:18:58 -08:00 |
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Howard Mao
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e80340198a
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use implicit parameters for ALU
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2015-11-30 17:35:33 -08:00 |
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Howard Mao
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9256239206
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implement support for multiple RoCC accelerators
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2015-11-26 12:46:01 -08:00 |
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Howard Mao
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58b0a86834
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some modifications to AccumulatorExample
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2015-11-26 08:48:19 -08:00 |
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Howard Mao
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b0a06a77db
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fix a few Chisel3 compat issues
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2015-11-20 13:33:15 -08:00 |
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Howard Mao
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19daee10f0
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use default constructors for IOMSHR acquire construction
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2015-11-12 15:54:05 -08:00 |
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Howard Mao
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0b7c828b5d
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go back to using standard LockingArbiter
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2015-10-21 09:15:51 -07:00 |
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Howard Mao
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c68d9f8137
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make ProbeUnit state machine easier to understand
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2015-10-20 23:25:23 -07:00 |
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Howard Mao
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19656e4abe
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make sure to generate release from clean coh state on probe miss
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2015-09-30 16:58:18 -07:00 |
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Howard Mao
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2f3d15675c
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fix DataArray writemask in L1D
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2015-09-28 16:02:39 -07:00 |
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Howard Mao
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4bda6b6757
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fix bug in tlb refill
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2015-09-26 21:27:36 -07:00 |
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Howard Mao
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6bf8f41cef
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make sure passthrough requests are treated as vm_enabled = false
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2015-09-26 20:29:51 -07:00 |
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Howard Mao
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a66bdb1956
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replace remaining uses of Vec.fill
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2015-09-24 17:53:26 -07:00 |
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Howard Mao
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9eb988a4c6
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make sure access to invalid physical address treated as exception
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2015-09-22 10:11:43 -07:00 |
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Howard Mao
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16c748576a
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don't mux data_word_bypass between IOMSHR and cache
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2015-09-22 10:10:57 -07:00 |
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Howard Mao
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d89bcd3922
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modify csr file to bring in line with HTIF changes
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2015-09-22 10:10:57 -07:00 |
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Howard Mao
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382faba4a6
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Implement bypassing L1 data cache for MMIO
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2015-09-22 10:10:57 -07:00 |
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