Howard Mao
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58b0a86834
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some modifications to AccumulatorExample
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2015-11-26 08:48:19 -08:00 |
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Andrew Waterman
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e203b8b378
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Make ALU generic for zscale
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2015-11-24 19:17:07 -08:00 |
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Andrew Waterman
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5294e94794
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Remove CSR back pressure ability
We were using it for IPIs, but no longer need it.
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2015-11-24 18:28:14 -08:00 |
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Andrew Waterman
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4616db4695
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Make RegFile/ImmGen usable by zscale
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2015-11-24 18:27:07 -08:00 |
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Andrew Waterman
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6d1bf5c014
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Use generic LoadGen/StoreGen
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2015-11-24 18:13:33 -08:00 |
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Sagar Karandikar
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65632c875a
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Merge branch 'master' into rocc-fpu-port
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2015-11-21 02:24:38 -08:00 |
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Howard Mao
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b0a06a77db
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fix a few Chisel3 compat issues
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2015-11-20 13:33:15 -08:00 |
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Yunsup Lee
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94d2dd3053
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-16 23:29:25 -08:00 |
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Andrew Waterman
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0f092b9b59
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Remove IPI network
This is now provided via MMIO.
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2015-11-16 21:51:43 -08:00 |
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Yunsup Lee
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5e2698adbc
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-14 16:44:55 -08:00 |
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Yunsup Lee
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213c1a4c81
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fix fdiv/fsqrt control bug in fpu
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2015-11-14 16:43:15 -08:00 |
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Yunsup Lee
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4dd097d156
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-14 14:52:13 -08:00 |
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Yunsup Lee
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3c3c946755
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move to new version of hardfloat
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2015-11-14 14:49:17 -08:00 |
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Yunsup Lee
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608e4b2851
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-12 20:44:25 -08:00 |
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Howard Mao
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19daee10f0
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use default constructors for IOMSHR acquire construction
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2015-11-12 15:54:05 -08:00 |
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Andrew Waterman
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59ca373146
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Merge pull request #18 from jackkoenig/master
Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
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2015-11-08 22:38:01 -08:00 |
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jackkoenig
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1e259a55da
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Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
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2015-11-08 21:16:31 -08:00 |
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Yunsup Lee
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df5daaa72e
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-06 23:57:42 -08:00 |
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Andrew Waterman
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2f515b2af6
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Reduce critical path for fdiv valid signal
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2015-11-06 23:28:31 -08:00 |
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Colin Schmidt
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86d67051b2
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Merge commit 'e31be75' into rocc-fpu-port
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2015-10-26 16:29:51 -07:00 |
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Yunsup Lee
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c7235fecb5
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further state optimization in CSRfile when not UseVM
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2015-10-25 10:23:46 -07:00 |
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Colin Schmidt
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652fb393a3
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-10-22 16:38:28 -07:00 |
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Jim Lawson
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0c587704a7
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Add ability to generate libraryDependency on cde.
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2015-10-22 11:37:20 -07:00 |
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Henry Cook
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4f8468b60f
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depend on external cde library
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2015-10-21 18:19:23 -07:00 |
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Colin Schmidt
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942f6a7d7f
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Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port
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2015-10-21 17:18:20 -07:00 |
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Colin Schmidt
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97f29b1618
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-10-21 11:33:42 -07:00 |
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Howard Mao
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0b7c828b5d
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go back to using standard LockingArbiter
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2015-10-21 09:15:51 -07:00 |
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Howard Mao
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c68d9f8137
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make ProbeUnit state machine easier to understand
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2015-10-20 23:25:23 -07:00 |
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Henry Cook
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1a1185be3f
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Vectorize ROCC and Tile memory interfaces
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2015-10-20 15:02:24 -07:00 |
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Colin Schmidt
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2cee8c8bec
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Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
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2015-10-18 13:09:17 -07:00 |
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Henry Cook
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6f8997bee9
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Minor refactor of StoreGen/AMOALU.
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2015-10-16 19:12:46 -07:00 |
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Henry Cook
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1441590c3b
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add enabled field to BTBParameters
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2015-10-16 19:12:39 -07:00 |
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Henry Cook
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969ecaecf8
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pass parameters to BuildRoCC
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2015-10-14 14:16:47 -07:00 |
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Henry Cook
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68cb54bc68
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refactor tilelink params
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2015-10-14 12:14:36 -07:00 |
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Henry Cook
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4508666d96
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log2ceil
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2015-10-06 18:22:47 -07:00 |
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Henry Cook
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8173695800
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added HasAddrMapParameters
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2015-10-06 18:22:40 -07:00 |
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Henry Cook
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84576650b5
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Removed all traces of params
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2015-10-05 21:48:05 -07:00 |
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Henry Cook
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69a4dd0a79
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refactor NASTI to not use param
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2015-10-02 14:20:47 -07:00 |
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Howard Mao
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19656e4abe
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make sure to generate release from clean coh state on probe miss
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2015-09-30 16:58:18 -07:00 |
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Andrew Waterman
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833909a2b5
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Chisel3 compatibility fixes
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2015-09-30 14:36:26 -07:00 |
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Andrew Waterman
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a7c908cb83
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Don't declare Reg inside of when
We haven't yet decided what the Chisel3 semantics for this will be.
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2015-09-30 12:43:36 -07:00 |
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Howard Mao
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2f3d15675c
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fix DataArray writemask in L1D
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2015-09-28 16:02:39 -07:00 |
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Andrew Waterman
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f8a7a80644
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Make perf counters optional
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2015-09-28 13:55:23 -07:00 |
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Andrew Waterman
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5e88ead984
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Add pseudo-ops to instructions.scala
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2015-09-28 11:52:27 -07:00 |
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Andrew Waterman
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b93a94597c
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Remove needless control logic
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2015-09-27 13:31:52 -07:00 |
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Howard Mao
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4bda6b6757
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fix bug in tlb refill
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2015-09-26 21:27:36 -07:00 |
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Howard Mao
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6bf8f41cef
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make sure passthrough requests are treated as vm_enabled = false
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2015-09-26 20:29:51 -07:00 |
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Andrew Waterman
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c3fff12ff0
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Revert "replace remaining uses of Vec.fill"
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
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2015-09-25 17:09:06 -07:00 |
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Andrew Waterman
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0bfb2962a6
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Assume coh.isRead returns true for store-conditional
This requires an uncore update.
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2015-09-25 15:26:11 -07:00 |
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Howard Mao
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a66bdb1956
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replace remaining uses of Vec.fill
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2015-09-24 17:53:26 -07:00 |
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