Yunsup Lee
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d38603a4ee
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change number of tlb entries
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2012-03-16 17:08:03 -07:00 |
|
Henry Cook
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b5fa86e844
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4-way associative by default
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2012-03-14 17:51:12 -07:00 |
|
Yunsup Lee
|
b19d783fbd
|
add vector irq handler
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2012-03-14 14:15:28 -07:00 |
|
Yunsup Lee
|
040d62f372
|
refactored vector exception handling interface
|
2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
5655dbd5da
|
add vvcfg and vtcfg instructions
|
2012-03-13 23:45:34 -07:00 |
|
Andrew Waterman
|
1788c34113
|
parameterize broadcast hub by # of tiles
|
2012-03-13 17:12:01 -07:00 |
|
Andrew Waterman
|
8ffdac9526
|
fix D$ store-upgrade bug
loads to the same address as stores that cause an upgrade
could return the old value
|
2012-03-10 15:50:10 -08:00 |
|
Yunsup Lee
|
44ff22a26f
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vector exception handler now handles prefetches correctly
|
2012-03-10 12:54:36 -08:00 |
|
Yunsup Lee
|
a1b30282dd
|
major refactoring on vector exception interface
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2012-03-09 01:09:22 -08:00 |
|
Andrew Waterman
|
941873bad1
|
coherence hub fixes
|
2012-03-07 21:03:44 -08:00 |
|
Andrew Waterman
|
499c5b4a2e
|
automatically infer MEM_TAG_BITS
|
2012-03-06 15:49:28 -08:00 |
|
Yunsup Lee
|
dba99e07a9
|
set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4
|
2012-03-06 08:54:21 -08:00 |
|
Andrew Waterman
|
5f12990dfb
|
support memory transaction aborts
|
2012-03-06 00:35:02 -08:00 |
|
Yunsup Lee
|
d4ec7ff4d9
|
refined vector exception interface
|
2012-03-03 16:11:54 -08:00 |
|
Yunsup Lee
|
e28a551368
|
refactor code related to vector exceptions
- revisied interfaces
- new instructions
|
2012-03-03 15:15:00 -08:00 |
|
Henry Cook
|
1b3307df32
|
Removed has_data fields from all coherence messages, increased message type names to compensate
|
2012-03-02 23:51:53 -08:00 |
|
Yunsup Lee
|
1054cec087
|
add vec countq interface
|
2012-03-02 00:43:32 -08:00 |
|
Yunsup Lee
|
a8ef5e9e27
|
change NMSHR when HAVE_VEC is true
|
2012-03-01 01:07:47 -08:00 |
|
Yunsup Lee
|
6847160343
|
refactor arbiter priorities
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2012-03-01 00:22:34 -08:00 |
|
Andrew Waterman
|
012da6002e
|
replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
|
2012-02-29 03:10:47 -08:00 |
|
Andrew Waterman
|
2b1c07c723
|
replace ioDCache with ioMem
|
2012-02-27 18:36:09 -08:00 |
|
Andrew Waterman
|
1d41a41afa
|
remove extraneous constants
|
2012-02-27 17:49:48 -08:00 |
|
Andrew Waterman
|
e12b9eae93
|
remove ext_mem interface
hindsight is 20/20
|
2012-02-26 18:53:39 -08:00 |
|
Yunsup Lee
|
f3bb02b2ea
|
refactored dmem arbiter
|
2012-02-26 17:38:08 -08:00 |
|
Daiwei Li
|
569698b824
|
dtlb now arbitrates between cpu, vec, and vec pf
|
2012-02-25 22:05:30 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
946e0c6e4e
|
add vector exception infrastructure
|
2012-02-25 16:37:56 -08:00 |
|
Andrew Waterman
|
4121fb178c
|
clean up mul/div interface; use VU mul if HAVE_VEC
|
2012-02-24 19:22:35 -08:00 |
|
Henry Cook
|
62837537f4
|
Improved TileIO organization, beginnings of hub implementation
|
2012-02-22 18:24:52 -08:00 |
|
Henry Cook
|
24a32c2811
|
Refining tilelink interface
|
2012-02-22 12:15:47 -08:00 |
|
Henry Cook
|
18bd0c232b
|
Added coherence message type enums
|
2012-02-22 12:15:47 -08:00 |
|
Andrew Waterman
|
7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Henry Cook
|
619929eba1
|
Added coherence tile function defs, with traits and constants
|
2012-02-16 00:16:45 -08:00 |
|
Andrew Waterman
|
fc5ba769da
|
disable vector unit by default
|
2012-02-15 18:58:41 -08:00 |
|
Andrew Waterman
|
c13524ad3a
|
fix vcmdq full replay logic
|
2012-02-15 17:49:12 -08:00 |
|
Yunsup Lee
|
6bdf9dc513
|
hwacha integration: now it compiles correctly!
|
2012-02-14 23:34:57 -08:00 |
|
Andrew Waterman
|
c78c738f60
|
minor cleanups
|
2012-02-13 03:13:49 -08:00 |
|
Yunsup Lee
|
f47d888feb
|
vvcfgivl and vsetvl works
|
2012-02-09 02:35:21 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
|
2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
|
8b6b0f5367
|
add external memory request interface for vec unit
|
2012-02-08 22:30:45 -08:00 |
|
Yunsup Lee
|
9285a52f25
|
initial vu integration
|
2012-02-08 21:43:45 -08:00 |
|
Andrew Waterman
|
e9da2cf66a
|
improve id/ex datapath
move operand selection into decode stage; simplify bypassing
|
2012-02-08 06:47:26 -08:00 |
|
Andrew Waterman
|
5403d069e9
|
add fp loads/stores
|
2012-02-07 23:54:25 -08:00 |
|
Andrew Waterman
|
01a156eb98
|
make # of dcache lines configurable
|
2012-02-01 21:11:45 -08:00 |
|
Andrew Waterman
|
a5a020f97b
|
update chisel and remove SRAM_READ_LATENCY
|
2012-01-23 20:59:38 -08:00 |
|
Henry Cook
|
8623d58724
|
split into two caches, compiles
|
2012-01-18 17:09:35 -08:00 |
|
Andrew Waterman
|
0369b05deb
|
move replays to writeback stage
|
2012-01-17 21:12:31 -08:00 |
|
Andrew Waterman
|
eb657dd250
|
reduce superfluous replays
we only replay after a cache miss if we mis-scheduled the use of a load.
|
2012-01-01 21:28:38 -08:00 |
|
Andrew Waterman
|
b5a8b6dc73
|
fix divider for RV32
|
2011-12-19 16:57:53 -08:00 |
|