riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
1,051 Commits 1 Branch 0 Tags 13 MiB
cae4265f3b
Commit Graph

1028 Commits

Author SHA1 Message Date
Henry Cook
8173695800 added HasAddrMapParameters 2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Henry Cook
69a4dd0a79 refactor NASTI to not use param 2015-10-02 14:20:47 -07:00
Howard Mao
19656e4abe make sure to generate release from clean coh state on probe miss 2015-09-30 16:58:18 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
a7c908cb83 Don't declare Reg inside of when 
We haven't yet decided what the Chisel3 semantics for this will be.
 2015-09-30 12:43:36 -07:00
Howard Mao
2f3d15675c fix DataArray writemask in L1D 2015-09-28 16:02:39 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Andrew Waterman
5e88ead984 Add pseudo-ops to instructions.scala 2015-09-28 11:52:27 -07:00
Andrew Waterman
b93a94597c Remove needless control logic 2015-09-27 13:31:52 -07:00
Howard Mao
4bda6b6757 fix bug in tlb refill 2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef make sure passthrough requests are treated as vm_enabled = false 2015-09-26 20:29:51 -07:00
Andrew Waterman
c3fff12ff0 Revert "replace remaining uses of Vec.fill" 
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
 2015-09-25 17:09:06 -07:00
Andrew Waterman
0bfb2962a6 Assume coh.isRead returns true for store-conditional 
This requires an uncore update.
 2015-09-25 15:26:11 -07:00
Howard Mao
a66bdb1956 replace remaining uses of Vec.fill 2015-09-24 17:53:26 -07:00
Howard Mao
9eb988a4c6 make sure access to invalid physical address treated as exception 2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a don't mux data_word_bypass between IOMSHR and cache 2015-09-22 10:10:57 -07:00
Howard Mao
d89bcd3922 modify csr file to bring in line with HTIF changes 2015-09-22 10:10:57 -07:00
Howard Mao
382faba4a6 Implement bypassing L1 data cache for MMIO 2015-09-22 10:10:57 -07:00
Andrew Waterman
e72e5a34b5 Fix storage of SP values in DP registers 
The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s.  This meant that an FSD + FLD of that register
would not restore the value properly.

Also, minor code cleanup.
 2015-09-21 12:20:44 -07:00
Christopher Celio
76bf1da310 [commitlog] zero-extend SP write-back values 2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c [commitlog] don't print out writebacks to x0 2015-09-15 16:47:26 -07:00
Christopher Celio
e22bf02a80 [commitlog] CSR's cycle optionally set to instret 
- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
 2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262 [commitlog] Added privilege-level to output 2015-09-15 16:47:24 -07:00
Christopher Celio
53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback 2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c [commitlog] Initial commit log for integer working 2015-09-15 15:59:03 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Colin Schmidt
d292b6cb13 don't connect rocc-fpu-port without rocc accel 2015-09-08 14:44:12 -07:00
Colin Schmidt
cab12635f8 Merge master into rocc-fpu-port 
ebb33f2f4b658211960a4c6c023c139420c67212
 2015-08-06 08:03:10 -07:00
Andrew Waterman
1718333f83 Don't use Vec as lvalue 2015-08-05 15:29:33 -07:00
Andrew Waterman
546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman
d4c94c6566 Chisel3 has different Vec semantics 
Vec(a, b) := c doesn't modify a and b in chisel3.
 2015-08-03 19:08:00 -07:00
Andrew Waterman
c345d72af4 Chisel3: Flip order of := and <> 2015-08-03 18:53:09 -07:00
Andrew Waterman
ef319edc84 Bits -> UInt 2015-08-02 21:03:42 -07:00
Andrew Waterman
52fc34a138 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:11:25 -07:00
Andrew Waterman
6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
Andrew Waterman
6d7cc37e87 Specify some uninferrable widths 
It's really scary that Chisel2 passed this stuff.
 2015-07-31 14:23:52 -07:00
Andrew Waterman
45cf64dbd7 Use UInt instead of Vec[Bool] 2015-07-31 04:59:45 -07:00
Andrew Waterman
57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Henry Cook
d2a594fb57 new junctions repo has mem size constants 2015-07-29 18:05:54 -07:00
Andrew Waterman
ce161b83e3 Chisel3 compatibility: avoid subword assignment 2015-07-29 15:03:13 -07:00
Andrew Waterman
c8c312e860 minor btb cleanup 2015-07-29 15:03:01 -07:00
Andrew Waterman
a2fdcdcaef Use Seq, not Iterable, when traversal order matters 2015-07-29 00:24:58 -07:00
Andrew Waterman
431dd2219b Another Bits -> BitPat 2015-07-28 20:13:56 -07:00
Andrew Waterman
049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares 
This one's hella ugly, but for the time being, idgaf.
 2015-07-28 02:48:49 -07:00
Andrew Waterman
f2dcc40e67 Chisel3 compatibility changes 2015-07-27 12:42:20 -07:00
Andrew Waterman
ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman
e9433ee01e Minor cleanup 2015-07-22 17:38:08 -07:00
Andrew Waterman
b4e4ceed3d Factor out some more hazard detection code 2015-07-22 15:52:13 -07:00
Andrew Waterman
bd785e7d19 Factor out common hazard detection code 2015-07-22 15:46:20 -07:00
Andrew Waterman
cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
5b7f3c3006 Don't use clone 2015-07-15 17:30:50 -07:00
Henry Cook
f5b3649b73 Merge commit 'd819fb28c3370747475d7c5f4b641723cab1fd0c' into rocc-fpu-port 2015-07-15 15:29:56 -07:00
Andrew Waterman
be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Andrew Waterman
a78e28523c Chisel3: Don't mix Mux types 2015-07-11 14:06:08 -07:00
Andrew Waterman
3233867390 Use Chisel3 SeqMem construct 2015-07-11 13:34:57 -07:00
Henry Cook
5ed2899e56 Merge pull request #10 from wsong83/fix 
L1 D$ writeback unit, reduce re-read data array
 2015-07-06 15:18:49 -07:00
Andrew Waterman
5362e2bbbd New machine-mode timer facility 2015-07-05 16:38:49 -07:00
Andrew Waterman
5e009ecc75 Fix an apparently benign PC sign-extension bug 2015-06-11 16:08:39 -07:00
Colin Schmidt
4b6cd7f3eb Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7 2015-06-03 15:51:53 -07:00
Wei Song
4db60d9e9d code clean in dcache, no need to check the condition twice. 2015-06-02 22:06:12 +01:00
Wei Song
b6e68773fd nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array. 2015-05-30 16:25:27 +01:00
Andrew Waterman
6a9390c50e Avoid spurious D$ assertion failures 
For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
 2015-05-19 03:00:53 -07:00
Andrew Waterman
f460cb6c54 Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00
Andrew Waterman
254498042a Fix Split for 0-width wires 2015-05-18 18:23:17 -07:00
Andrew Waterman
d31b26c342 Clean up handling of icache's io.cpu.npc signal 2015-05-18 18:22:48 -07:00
Christopher Celio
b09832f1b5 ICache now returns the "next PC" signal. 
useful for other modules that need access to the fetch PC on the
   cycle it is sent to the SRAM.
 2015-05-07 04:53:05 -07:00
Colin Schmidt
c746ef8702 fix bug in rocc port resp for FPtoInt instructions 2015-05-04 11:20:55 -07:00
Yunsup Lee
b9fb1bb46e Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-04-29 00:43:53 -07:00
Colin Schmidt
a37fad2e9b Merge branch 'retimeable-frontend' into rocc-fpu-port 2015-04-22 14:23:52 -07:00
Colin Schmidt
1f410ac42c move fetch buffer into frontend to allow retiming 2015-04-22 11:26:03 -07:00
Henry Cook
a315fe93c1 simplify ClientMetadata.makeRelease 2015-04-20 10:46:24 -07:00
Albert Ou
ca5b3d988d Merge branch 'master' into rocc-fpu-port 2015-04-19 15:00:00 -07:00
Henry Cook
3048f4785a HeaderlessTileLinkIO -> ClientTileLinkIO 2015-04-17 16:56:53 -07:00
Colin Schmidt
73fa28521d Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port 2015-04-16 15:22:08 -07:00
Henry Cook
49f1c0aa7b moved ecc lib to uncore 2015-04-13 15:58:10 -07:00
Henry Cook
91e882e3f8 Use HeaderlessTileLinkIO 2015-04-13 15:58:10 -07:00
Christopher Celio
517d0d4b89 feedback on PR 2015-04-12 18:44:03 -07:00
Christopher Celio
4d6ebded02 Added assert to nbdcache 2015-04-11 02:58:34 -07:00
Christopher Celio
a564f08702 Rename dmem.sret signal to more accurate invalidate_lr 2015-04-11 02:26:33 -07:00
Christopher Celio
8fc2d38ca9 Removed unnecessary signal in CSRIO 2015-04-11 02:20:34 -07:00
Christopher Celio
2f88c5ca9d Renamed PCR to CSR 2015-04-11 02:16:44 -07:00
Christopher Celio
11dbd4221a Fixed front-end to support four-wide fetch. 2015-04-10 17:53:47 -07:00
Colin Schmidt
bd72db92c1 update rocc port to use fdiv/sqrt 2015-04-07 15:02:02 -07:00
Colin Schmidt
887a8de189 Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port 2015-04-06 13:48:44 -07:00
Andrew Waterman
9ade0e41cc Integrate divide/sqrt unit 2015-04-04 16:39:17 -07:00
Andrew Waterman
fe27b9b1b2 Support writing sstatus.fs even without an FPU 2015-04-04 15:20:18 -07:00
Andrew Waterman
bce62d5774 Update PTE format to reflect reserved bits 2015-04-04 15:19:15 -07:00
Colin Schmidt
a369d8f17f Add fpu port to the rocc interface 2015-04-02 01:30:11 -07:00
Andrew Waterman
d912ea265e New virtual memory implementation (Sv39) 2015-03-27 16:20:59 -07:00
Andrew Waterman
faada5f110 Mask off LSBs of sepc/mepc/stvec 
Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
 2015-03-25 00:20:58 -07:00
Andrew Waterman
543ac91cf2 Misaligned fetches can't happen at the I$ anymore 
They are caught before the I$ ever sees them, so leverage that fact.
 2015-03-24 23:55:43 -07:00
Andrew Waterman
90b31586ff Misc. CSR fixes/improvements 
- Support RV32 mstatus register
- Don't ignore mstatus.stie bit
- Support custom M-mode R/W CSRs for Raven chip
 2015-03-24 23:50:18 -07:00
Andrew Waterman
822698b567 support disabling supervisor mode (via UseVM parameter) 2015-03-24 19:32:45 -07:00
Andrew Waterman
0332c1e7fe Reduce latency of page table walks 
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
 2015-03-24 18:58:38 -07:00
Andrew Waterman
31d17cbf86 Hard-wire LSB of JALR to 0, as sent to BTB 2015-03-21 00:16:34 -07:00
Yunsup Lee
53617d6df5 fix long-standing dcache bug 
have to initialize register, if it is used the same cycle it is begin written
 2015-03-17 21:45:17 -07:00
Yunsup Lee
5b4653b621 fix rocc exception/s bit 2015-03-17 05:08:23 -07:00
Andrew Waterman
66388be1ce Merge [shm]call into ecall, [shm]ret into eret 2015-03-17 02:24:41 -07:00
Andrew Waterman
2c875555a2 Separate exception return control from exception control 2015-03-17 00:14:32 -07:00
Andrew Waterman
e85c54cc4b New privileged ISA implementation 2015-03-14 02:49:07 -07:00
Yunsup Lee
ebbd14254c uncached port should be a HeaderlessUncachedTileLinkIO type 2015-03-13 02:12:23 -07:00
Henry Cook
51e4cd7616 Added UncachedTileLinkIO port to RocketTile, simplify arbitration 2015-03-12 16:30:04 -07:00
Yunsup Lee
ea018b3d84 stall rocket decode when not rocc ready 2015-03-11 22:33:03 -07:00
Colin Schmidt
e293d89035 fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/ 2015-03-10 10:28:05 -07:00
Henry Cook
95aa295c39 Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS 2015-03-09 16:34:43 -07:00
Henry Cook
b36d751250 sret bugfix: bypass arbiter 2015-03-05 13:14:16 -08:00
Christopher Celio
06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache 2015-03-03 16:50:41 -08:00
Christopher Celio
5d07733057 Removed TLBPTWIO from the io.cpu bundle for icache/dcache 2015-03-03 16:40:39 -08:00
Henry Cook
1e0c16c557 new metadata api 2015-02-28 17:00:32 -08:00
Henry Cook
0b131173e6 WritebackUnit multibeat control logic bugfix 2015-02-16 10:59:57 -08:00
Henry Cook
aa46b8b72d Slightly refactor TLBResp 2015-02-03 19:32:37 -08:00
Stephen Twigg
3d35ccd401 Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:10:54 -08:00
Henry Cook
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Scott Beamer
00e074cdd9 fixes slight bug for non-power of 2 number of ras entries 2015-01-29 15:29:25 -08:00
Andrew Waterman
a98127c09e Merge branch 'ss-frontend' 2015-01-04 20:26:38 -08:00
Andrew Waterman
b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman
87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
Andrew Waterman
2aee85cb11 Flush pipeline from MEM stage 
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
 2015-01-04 16:40:16 -08:00
Andrew Waterman
94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00
Henry Cook
1cb65d5ec1 %s/master/manager/g 2014-12-29 22:56:18 -08:00
Henry Cook
77e5e6b561 refill bug 2014-12-17 19:29:28 -08:00
Henry Cook
08dcf4c6ca refactor cache params 2014-12-17 14:28:05 -08:00
Henry Cook
d29793d1f7 cleanup CoherenceMetadata and coherence params 2014-12-15 19:23:38 -08:00
Henry Cook
c9320862ae add l2 dmem signal to rocc 2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b multibeat TL; passes all tests 2014-12-12 16:54:33 -08:00
Christopher Celio
f19b3ca43e Deleted extra spaces at EOL in ctrl.scala 2014-11-16 22:04:33 -08:00
Christopher Celio
6749f67b7f Fixed BHT update error. 
- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
 2014-11-16 22:02:27 -08:00
Henry Cook
b7b2923bff Cleanup MSHR internal bundles 2014-11-11 18:18:35 -08:00
Henry Cook
c9e7874818 Major tilelink revision for uncached message types 2014-11-11 17:36:48 -08:00
Christopher Celio
fea31d2167 Significant changes and fixes to BTB for superscalar fetch. 
- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
 2014-11-11 03:34:05 -08:00
Henry Cook
bf901e4bca Remove master_xact_id from Release 2014-11-06 12:09:45 -08:00
Christopher Celio
3be3cd7731 Fixed error with icache/btb resp mask. 2014-11-03 01:13:22 -08:00
Christopher Celio
08d2c13330 Fixed btb/icache bugs regarding resp mask, fw==1 2014-10-20 18:45:23 -07:00
Christopher Celio
91efdc379b Merge remote-tracking branch 'origin/master' into ss-frontend 
Also fixed bridx logic and zero-width wire logic.

Conflicts:
	src/main/scala/btb.scala
 2014-10-14 18:10:29 -07:00
Andrew Waterman
7bb7299018 Don't pollute BTB with PC+4 target predictions 2014-10-14 17:28:37 -07:00
Christopher Celio
59eb7d194d Finalize superscalar btb. 2014-10-03 16:08:08 -07:00
Andrew Waterman
cde7c9d869 simplify CSR decoding code 2014-10-03 14:31:26 -07:00
Christopher Celio
99614e37aa Merge remote-tracking branch 'origin/master' into ss-frontend 
Conflicts:
	src/main/scala/btb.scala
	src/main/scala/core.scala
 2014-10-03 04:22:58 -07:00
Christopher Celio
9cc35dee9a Returned history update to fetch. 
- Global history only contains branches.
   - Only update BHT and history on BTB hits.
   - Gate off speculative update on stall or icmiss.
   - Fixed bug where BHT updates were delayed a cycle.
 2014-09-29 21:41:07 -07:00
Christopher Celio
8ccd07cfeb Moved updating global history from fetch to decode. 
- No longer update global history in fetch stage.
   - Only update global history when instruction is a branch.
   - Does allow for the possibility of back-to-back branches to see
     slightly different histories on subsequent executions.
 2014-09-28 05:16:36 -07:00
Christopher Celio
681b43f398 Bug fixes with global history register. 
- Updated in fetch speculatively.
      * Updates gated off by cpu.resp.fire().
      * BTB direction factored into history update.
   - All branches update the BHT.
   - Each instruction carries history; index into BHT is recomputed by
     passing in mem_reg_pc.
 2014-09-26 10:39:57 -07:00
Christopher Celio
a71bdbbc54 Update history register in fetch speculatively 2014-09-26 05:42:08 -07:00
Christopher Celio
f917810061 Removed RocketCoreParameters from use. 
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
   - This conflicts with other cores which uses nbdcache.
   - RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
 2014-09-26 05:14:50 -07:00
Christopher Celio
868e747656 Factored out Rocket specifics from CoreParameters 
- Added new RocketCoreParameters
   - Other cores using Rocket as a library will no longer conflict against
      Rocket's requires().
 2014-09-25 18:52:58 -07:00
Henry Cook
8eb64205f5 bug fix for nbdcache s2_data 2014-09-25 12:00:20 -07:00
Henry Cook
b55c38cdc7 Remove spurious vec consts 2014-09-25 12:00:20 -07:00