Howard Mao
bfdf5a538a
Separate memory interconnect from IO interconnect.
...
Since we're separating memory and MMIO traffic in the L1 to L2 network,
we won't need to route between memory and MMIO at the AXI interconnect.
This means we can have separate (and simpler) AXI interconnects for
each. One consequence of this is that the starting address of the IO
interconnect can no longer be assumed to be 0 by default.
2016-02-02 13:14:04 -08:00
Andrew Waterman
a56a502ced
Add missing cloneType method
...
@zhemao
2016-01-23 21:36:16 -08:00
Howard Mao
19c526de59
move ReorderQueue and DecoupledHelper in from uncore
2016-01-21 15:37:07 -08:00
Howard Mao
6a0352c6d0
fix up SmiMem
2016-01-20 23:25:16 -08:00
Andrew Waterman
335fb73120
Chisel3 compatibility fix
...
No need for a Vec here.
2016-01-15 15:17:16 -08:00
Howard Mao
c8fa7c43a9
fix Chisel3 deprecation warnings
2016-01-14 13:38:00 -08:00
Howard Mao
5d7b5b219f
lowercase SMI to Smi
2016-01-11 16:18:38 -08:00
Howard Mao
9d2637c2c7
support empty submaps in interconnect generator
2016-01-07 11:55:24 -08:00
Howard Mao
673f73b051
add support for AXI streaming protocol
2016-01-05 20:04:49 -08:00
Howard Mao
c57639b23f
reverse order of RWX bits for compatibility
2015-12-05 00:27:24 -08:00
Howard Mao
7083576156
fix typo in NastiErrorSlave
2015-11-26 12:57:04 -08:00
Howard Mao
e7e281275a
implement MultiChannel routing in a specialized (and more performant) way
2015-11-18 17:01:52 -08:00
Howard Mao
3e906c8620
shave off channel select bits in MultiChannel router
2015-11-02 22:39:50 -08:00
Howard Mao
096dbb3c2d
get rid of NastiTopInterconnect
2015-10-26 14:14:53 -07:00
Howard Mao
5440d6c2ae
balance MultiChannel router correctly
2015-10-26 12:23:03 -07:00
Howard Mao
3270d17ad3
add MultiChannel routing to Nasti interconnect generator
2015-10-26 12:16:17 -07:00
Jim Lawson
8fe4917d8e
Add ability to generate libraryDependency on cde.
2015-10-22 09:52:26 -07:00
Henry Cook
9c3cd8f9fe
depend on external cde library
2015-10-21 18:16:03 -07:00
Howard Mao
11eacda84a
generalize NastiReadDataArbiter
2015-10-20 18:36:19 -07:00
Yunsup Lee
cedef98045
fix NASTI -> MemIO converter bug
2015-10-19 21:43:59 -07:00
Henry Cook
da5fe84f53
Merge branch 'param-refactor'
2015-10-14 00:14:13 -07:00
Howard Mao
2fee3fd0fd
make sure NASTI -> SMI converter still works if words per beat is 1
2015-10-13 12:44:48 -07:00
Henry Cook
166df221ad
added HasAddrMapParameters
2015-10-06 18:15:16 -07:00
Henry Cook
adcd77db36
Removed all traces of params
2015-10-05 20:33:55 -07:00
Henry Cook
970445a26a
refactor MemIO to not use params
2015-10-02 15:37:41 -07:00
Henry Cook
39a749843c
refactor NASTI to not use param; new AddrMap class
2015-10-02 14:19:51 -07:00
Andrew Waterman
a08872c0e9
val -> def in static object
2015-09-25 17:05:28 -07:00
Andrew Waterman
e75674c0cb
Revert "replace remaining uses of Vec.fill"
...
This reverts commit 16dca2186b95945ad2ba5f906113101de0726617.
2015-09-25 17:05:07 -07:00
Howard Mao
a9c6cced2d
fix bug in NASTIArbiter
2015-09-25 11:03:24 -07:00
Howard Mao
2e63fb291a
put sensible defaults for NASTI channel constructors
2015-09-25 10:09:25 -07:00
Howard Mao
88b15dba60
replace remaining uses of Vec.fill
2015-09-24 17:51:38 -07:00
Howard Mao
e3d2207c72
Chisel3 compat: merge NASTIMasterIO and NASTISlaveIO so we do not depend on flip() modifying the object
2015-09-24 16:57:50 -07:00
Howard Mao
ee65f6a84d
get rid of Vec.fill in IOs
2015-09-22 10:30:09 -07:00
Howard Mao
64ab45e2e4
add RWX permission bits to address map
2015-09-22 09:43:22 -07:00
Howard Mao
27745204eb
ErrorSlave returns response of correct length for reads
2015-09-22 09:42:57 -07:00
Howard Mao
4db6124b2a
NASTIErrorSlave should print address
2015-09-18 09:42:41 -07:00
Howard Mao
4c3c3c630e
add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len
2015-09-10 17:55:10 -07:00
Howard Mao
6387d31c62
add comments and small fixes for NASTI and SMI
2015-09-10 17:33:48 -07:00
Howard Mao
8a8d52da4f
add convenient constructors for NASTI channels
2015-09-10 17:33:31 -07:00
Howard Mao
ede1ada053
Add converters and utilities for simpler peripheral interface (SMI)
2015-09-01 14:00:45 -07:00
Howard Mao
75ec7529af
implement NASTI Interconnect generating from configuration address map
2015-09-01 14:00:45 -07:00
Howard Mao
b046c57284
make NASTI -> MemIO converter compliant to AXI4 spec
2015-09-01 11:17:38 -07:00
Andrew Waterman
f7d9628de2
Avoid needless use of Vec
2015-08-27 09:40:52 -07:00
Andrew Waterman
3a1dad7994
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:40:24 -07:00
Andrew Waterman
2ff2b43c2c
Chisel3 compatibility: use >>Int instead of >>UInt
...
The latter doesn't contract widths anymore.
2015-08-04 13:13:44 -07:00
Andrew Waterman
e469785f5e
bump scala to 2.11.6
2015-08-03 19:51:17 -07:00
Andrew Waterman
d85c46bc60
Chisel3 bulk connect non-commutativity
2015-08-03 19:47:16 -07:00
Andrew Waterman
eb57433f43
Bits -> UInt
2015-07-30 23:57:53 -07:00
Henry Cook
c27945c094
source and build files. source code pulled from uncore and zscale repos
2015-07-29 18:02:58 -07:00
Henry Cook
6a44cd43fd
Update README.md
2015-07-28 16:20:18 -07:00
