Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

Howard Mao bfdf5a538a Separate memory interconnect from IO interconnect. ... Since we're separating memory and MMIO traffic in the L1 to L2 network, we won't need to route between memory and MMIO at the AXI interconnect. This means we can have separate (and simpler) AXI interconnects for each. One consequence of this is that the starting address of the IO interconnect can no longer be assumed to be 0 by default.		2016-02-02 13:14:04 -08:00
junctions	Separate memory interconnect from IO interconnect.	2016-02-02 13:14:04 -08:00