fix Chisel3 deprecation warnings
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5d7b5b219f
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c8fa7c43a9
@ -79,7 +79,7 @@ class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
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class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val master = new HastiMasterIO().flip
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val slaves = Vec(new HastiSlaveIO, amap.size).flip
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val slaves = Vec(amap.size, new HastiSlaveIO).flip
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}
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// skid buffer
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@ -149,7 +149,7 @@ class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModul
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class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val ins = Vec(new HastiSlaveIO, n)
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val ins = Vec(n, new HastiSlaveIO)
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val out = new HastiSlaveIO().flip
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}
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@ -219,8 +219,8 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])
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(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val masters = Vec(new HastiMasterIO, nMasters).flip
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val slaves = Vec(new HastiSlaveIO, addressMap.size).flip
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val masters = Vec(nMasters, new HastiMasterIO).flip
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val slaves = Vec(addressMap.size, new HastiSlaveIO).flip
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}
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val buses = List.fill(nMasters){Module(new HastiBus(addressMap))}
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@ -208,7 +208,7 @@ class MemDesser(w: Int)(implicit p: Parameters) extends Module // test rig side
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class MemIOArbiter(val arbN: Int)(implicit p: Parameters) extends MIFModule {
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val io = new Bundle {
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val inner = Vec(new MemIO, arbN).flip
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val inner = Vec(arbN, new MemIO).flip
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val outer = new MemIO
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}
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@ -263,7 +263,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) e
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/** Arbitrate among arbN masters requesting to a single slave */
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class NastiArbiter(val arbN: Int)(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val master = Vec(new NastiIO, arbN).flip
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val master = Vec(arbN, new NastiIO).flip
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val slave = new NastiIO
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}
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@ -388,7 +388,7 @@ class NastiRouter(nSlaves: Int, routeSel: UInt => UInt)(implicit p: Parameters)
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val io = new Bundle {
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val master = (new NastiIO).flip
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val slave = Vec(new NastiIO, nSlaves)
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val slave = Vec(nSlaves, new NastiIO)
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}
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val ar_route = routeSel(io.master.ar.bits.addr)
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@ -456,8 +456,8 @@ class NastiRouter(nSlaves: Int, routeSel: UInt => UInt)(implicit p: Parameters)
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class NastiCrossbar(nMasters: Int, nSlaves: Int, routeSel: UInt => UInt)
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(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val masters = Vec(new NastiIO, nMasters).flip
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val slaves = Vec(new NastiIO, nSlaves)
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val masters = Vec(nMasters, new NastiIO).flip
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val slaves = Vec(nSlaves, new NastiIO)
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}
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if (nMasters == 1) {
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@ -503,8 +503,8 @@ class NastiInterconnectIO(val nMasters: Int, val nSlaves: Int)
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(implicit p: Parameters) extends Bundle {
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/* This is a bit confusing. The interconnect is a slave to the masters and
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* a master to the slaves. Hence why the declarations seem to be backwards. */
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val masters = Vec(new NastiIO, nMasters).flip
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val slaves = Vec(new NastiIO, nSlaves)
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val masters = Vec(nMasters, new NastiIO).flip
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val slaves = Vec(nSlaves, new NastiIO)
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override def cloneType =
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new NastiInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
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}
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@ -54,7 +54,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
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io.out.paddr := haddr_reg
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io.out.pwrite := hwrite_reg(0)
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io.out.psel := (state != s_idle)
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io.out.psel := (state =/= s_idle)
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io.out.penable := (state === s_access)
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io.out.pwdata := io.in.hwdata
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io.in.hrdata := io.out.prdata
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@ -66,7 +66,7 @@ class PociBus(amap: Seq[UInt=>Bool]) extends Module
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{
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val io = new Bundle {
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val master = new PociIO().flip
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val slaves = Vec(new PociIO, amap.size)
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val slaves = Vec(amap.size, new PociIO)
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}
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val psels = PriorityEncoderOH(
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@ -59,7 +59,7 @@ class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral {
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class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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extends Module {
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val io = new Bundle {
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val in = Vec(new SmiIO(dataWidth, addrWidth), n).flip
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val in = Vec(n, new SmiIO(dataWidth, addrWidth)).flip
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val out = new SmiIO(dataWidth, addrWidth)
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}
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@ -22,7 +22,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
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val maybe_full = Reg(init=Bool(false))
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val enq_ptr = Counter(do_enq, entries)._1
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val (deq_ptr, deq_done) = Counter(do_deq, entries)
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when (do_enq != do_deq) { maybe_full := do_enq }
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when (do_enq =/= do_deq) { maybe_full := do_enq }
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val ptr_match = enq_ptr === deq_ptr
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val empty = ptr_match && !maybe_full
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@ -30,7 +30,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
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val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2)
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do_flow := empty && io.deq.ready
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val ram = SeqMem(data, entries)
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val ram = SeqMem(entries, data)
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when (do_enq) { ram.write(enq_ptr, io.enq.bits) }
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val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)
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@ -66,7 +66,7 @@ abstract class JunctionsAbstractLockingArbiter[T <: Data](typ: T, arbN: Int)
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extends Module {
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val io = new Bundle {
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val in = Vec(Decoupled(typ.cloneType), arbN).flip
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val in = Vec(arbN, Decoupled(typ.cloneType)).flip
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val out = Decoupled(typ.cloneType)
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}
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