lowercase SMI to Smi
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9d2637c2c7
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5d7b5b219f
@ -3,35 +3,35 @@ package junctions
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import Chisel._
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import cde.Parameters
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class SMIReq(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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class SmiReq(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val rw = Bool()
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val addr = UInt(width = addrWidth)
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val data = Bits(width = dataWidth)
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override def cloneType =
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new SMIReq(dataWidth, addrWidth).asInstanceOf[this.type]
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new SmiReq(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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/** Simple Memory Interface IO. Used to communicate with PCR and SCR
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* @param dataWidth the width in bits of the data field
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* @param addrWidth the width in bits of the addr field */
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class SMIIO(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val req = Decoupled(new SMIReq(dataWidth, addrWidth))
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class SmiIO(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val req = Decoupled(new SmiReq(dataWidth, addrWidth))
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val resp = Decoupled(Bits(width = dataWidth)).flip
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override def cloneType =
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new SMIIO(dataWidth, addrWidth).asInstanceOf[this.type]
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new SmiIO(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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abstract class SMIPeripheral extends Module {
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abstract class SmiPeripheral extends Module {
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val dataWidth: Int
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val addrWidth: Int
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lazy val io = new SMIIO(dataWidth, addrWidth).flip
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lazy val io = new SmiIO(dataWidth, addrWidth).flip
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}
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/** A simple sequential memory accessed through SMI */
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class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral {
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/** A simple sequential memory accessed through Smi */
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class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral {
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// override
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val addrWidth = log2Up(memDepth)
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@ -52,21 +52,21 @@ class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral {
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io.req.ready := !resp_valid
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}
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/** Arbitrate among several SMI clients
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/** Arbitrate among several Smi clients
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* @param n the number of clients
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* @param dataWidth SMI data width
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* @param addrWidth SMI address width */
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class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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* @param dataWidth Smi data width
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* @param addrWidth Smi address width */
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class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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extends Module {
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val io = new Bundle {
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val in = Vec(new SMIIO(dataWidth, addrWidth), n).flip
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val out = new SMIIO(dataWidth, addrWidth)
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val in = Vec(new SmiIO(dataWidth, addrWidth), n).flip
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val out = new SmiIO(dataWidth, addrWidth)
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}
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val wait_resp = Reg(init = Bool(false))
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val choice = Reg(UInt(width = log2Up(n)))
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val req_arb = Module(new RRArbiter(new SMIReq(dataWidth, addrWidth), n))
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val req_arb = Module(new RRArbiter(new SmiReq(dataWidth, addrWidth), n))
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req_arb.io.in <> io.in.map(_.req)
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req_arb.io.out.ready := io.out.req.ready && !wait_resp
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@ -88,12 +88,12 @@ class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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io.out.resp.ready := io.in(choice).resp.ready
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}
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class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val ar = Decoupled(new NastiReadAddressChannel).flip
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val r = Decoupled(new NastiReadDataChannel)
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val smi = new SMIIO(dataWidth, addrWidth)
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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private val maxWordsPerBeat = nastiXDataBits / dataWidth
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@ -170,13 +170,13 @@ class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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}
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}
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class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val aw = Decoupled(new NastiWriteAddressChannel).flip
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val w = Decoupled(new NastiWriteDataChannel).flip
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val b = Decoupled(new NastiWriteResponseChannel)
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val smi = new SMIIO(dataWidth, addrWidth)
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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private val dataBytes = dataWidth / 8
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@ -185,7 +185,7 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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private val addrOffBits = addrWidth + byteOffBits
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assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits),
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"Nasti size must be >= SMI size")
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"Nasti size must be >= Smi size")
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val id = Reg(UInt(width = nastiWIdBits))
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val addr = Reg(UInt(width = addrWidth))
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@ -251,26 +251,26 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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when (io.b.fire()) { state := s_idle }
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}
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/** Convert Nasti protocol to SMI protocol */
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class SMIIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
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/** Convert Nasti protocol to Smi protocol */
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class SmiIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val smi = new SMIIO(dataWidth, addrWidth)
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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require(isPow2(dataWidth), "SMI data width must be power of 2")
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require(isPow2(dataWidth), "Smi data width must be power of 2")
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val reader = Module(new SMIIONastiReadIOConverter(dataWidth, addrWidth))
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val reader = Module(new SmiIONastiReadIOConverter(dataWidth, addrWidth))
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reader.io.ar <> io.nasti.ar
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io.nasti.r <> reader.io.r
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val writer = Module(new SMIIONastiWriteIOConverter(dataWidth, addrWidth))
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val writer = Module(new SmiIONastiWriteIOConverter(dataWidth, addrWidth))
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writer.io.aw <> io.nasti.aw
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writer.io.w <> io.nasti.w
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io.nasti.b <> writer.io.b
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val arb = Module(new SMIArbiter(2, dataWidth, addrWidth))
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val arb = Module(new SmiArbiter(2, dataWidth, addrWidth))
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arb.io.in(0) <> reader.io.smi
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arb.io.in(1) <> writer.io.smi
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io.smi <> arb.io.out
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