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Commit Graph

4505 Commits

Author SHA1 Message Date
Andrew Waterman
25fe46dc18 remove bug from dessert 2012-03-26 14:18:57 -07:00
Andrew Waterman
e2fe525fb6 remove bug from dessert 2012-03-26 14:18:57 -07:00
Yunsup Lee
e6b0e565de turn HAVE_VEC on 2012-03-26 01:21:39 -07:00
Andrew Waterman
5f53cd4ac1 reduce HTIF width 2012-03-25 23:49:59 -07:00
Andrew Waterman
ef505de017 reduce HTIF width 2012-03-25 23:49:45 -07:00
Andrew Waterman
4e6302fedc add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman
31f0b600fd add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman
5a00143035 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman
1666d3fbd7 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman
f62a02ab54 remove dumb stuff in top.scala 2012-03-25 21:30:01 -07:00
Andrew Waterman
a7ebea13fc add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman
88bf8a4f23 add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman
7fa93da4f5 add backup memory port (disabled for now) 2012-03-25 15:49:32 -07:00
Yunsup Lee
1f33f6bb58 HAVE_VEC is on 2012-03-24 20:54:43 -07:00
Andrew Waterman
86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
Andrew Waterman
3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
Andrew Waterman
54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
Yunsup Lee
65929a62e3 fix reset value for appvl 2012-03-22 15:32:04 -07:00
Yunsup Lee
aaed0241af get rid of vxcptwait 2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d now fence stalls in decode 2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40 fix irt counter bug regarding vector stuff 2012-03-20 17:09:54 -07:00
Yunsup Lee
7d7d7f49f9 change the tlb arbiter to a round robing one 2012-03-20 15:21:36 -07:00
Yunsup Lee
5f69c5a764 fix bug in coherence hub, specifically in abort handling logic 2012-03-20 02:16:28 -07:00
Yunsup Lee
1cddd5de56 fix amo locking up problem 2012-03-20 02:16:28 -07:00
Yunsup Lee
56cb9b7a63 fix bug in coherence hub, specifically in abort handling logic 2012-03-20 02:16:28 -07:00
Yunsup Lee
c036fff79c fix id interrupt signal 2012-03-19 15:13:57 -07:00
Yunsup Lee
0edea00166 now HAVE_VEC is true, since it passes the emulator 2012-03-19 03:10:00 -07:00
Yunsup Lee
264732556f fixes to match verilog X semantics 2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2 can now take interrupts on stalled instructions 2012-03-19 01:02:06 -07:00
Andrew Waterman
2ed0be65f9 fix RRArbiter 2012-03-19 00:19:33 -07:00
Yunsup Lee
ba06cd953e add chosen 2012-03-18 20:43:17 -07:00
Andrew Waterman
c4a91303fb update vector fence names and encoding 2012-03-18 20:42:38 -07:00
Yunsup Lee
2a01f558ba fix unmasked valid bug in ctrl_vec 2012-03-18 19:55:24 -07:00
Yunsup Lee
98e10ddc3c update vector exception instructions 2012-03-18 16:36:12 -07:00
Yunsup Lee
7493d55d3f add pf fault handling 2012-03-18 15:06:39 -07:00
Yunsup Lee
62ada5ea9e hookup vitlb ptw port 2012-03-17 23:01:06 -07:00
Yunsup Lee
b793d63182 no vector interrupt masking 2012-03-17 23:01:06 -07:00
Yunsup Lee
8a4f95e617 changes to xcpt handling 2012-03-17 17:50:37 -07:00
Yunsup Lee
8c50c81b81 drop vec_irq_aux pcr register, now everything goes through badvaddr 2012-03-17 14:03:57 -07:00
Yunsup Lee
3b4680a834 add vitlb exception port 2012-03-17 14:03:33 -07:00
Andrew Waterman
a47eeb9571 retime D$ bypass into beginning of EX stage 2012-03-16 18:35:54 -07:00
Andrew Waterman
6c26921766 reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
2012-03-16 18:35:54 -07:00
Yunsup Lee
d38603a4ee change number of tlb entries 2012-03-16 17:08:03 -07:00
Andrew Waterman
e38114e4b0 fix coherence bug
popping wrong store dependence queue
2012-03-16 01:24:07 -07:00
Andrew Waterman
f0157b9e2a fix coherence bug
popping wrong store dependence queue
2012-03-16 01:24:07 -07:00
Andrew Waterman
cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6 fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman
3129040bda use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00
Andrew Waterman
2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00