riscv/rocket-chip
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add vitlb exception port

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This commit is contained in:
Yunsup Lee 2012-03-17 14:03:33 -07:00
parent a47eeb9571
commit 3b4680a834
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/cpu.scala
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@ -159,7 +159,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
vu.io.imem_req.ready := Bool(true)
vu.io.imem_resp.valid := io.vimem.resp_val
vu.io.imem_resp.bits := io.vimem.resp_data
// handle vitlb.io.cpu.exception
vu.io.vitlb_exception := vitlb.io.cpu.exception
io.vimem.itlb_miss := vitlb.io.cpu.resp_miss
// hooking up vector command queues