add chosen

rocket/src/main/scala/cpu.scala

@@ -37,7 +37,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
   {
     vu = new vu()
     // cpu, vector prefetch, and vector use the DTLB
-    val dtlbarb = new hwacha.Arbiter(3)({new ioDTLB_CPU_req()})
+    val dtlbarb = new Arbiter(3)({new ioDTLB_CPU_req_bundle()})
     val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
     when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
 

rocket/src/main/scala/util.scala

@@ -163,6 +163,7 @@ class ioPipe[+T <: Data]()(data: => T) extends Bundle
 class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
   val in  = Vec(n) { (new ioDecoupled()) { data } }.flip
   val out = (new ioDecoupled()) { data }
+  val chosen = Bits(log2up(n), OUTPUT)
 }
 
 class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
@@ -174,8 +175,11 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
   }
 
   var dout = io.in(n-1).bits
-  for (i <- 1 to n-1)
+  var choose = Bits(n-1)
+  for (i <- 1 to n-1) {
     dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
+    choose = Mux(io.in(n-1-i).valid, Bits(n-1-i), choose)
+  }
 
   var vout = io.in(0).valid
   for (i <- 1 to n-1)
@@ -183,6 +187,7 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
 
   vout <> io.out.valid
   dout <> io.out.bits
+  choose <> io.chosen
 }
 
 class RRArbiter[T <: Data](n: Int)(data: => T) extends Component {