riscv/rocket-chip
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add chosen

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This commit is contained in:
Yunsup Lee 2012-03-18 20:43:08 -07:00
parent c4a91303fb
commit ba06cd953e
2 changed files with 7 additions and 2 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -37,7 +37,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
{
vu = new vu()
// cpu, vector prefetch, and vector use the DTLB
val dtlbarb = new hwacha.Arbiter(3)({new ioDTLB_CPU_req()})
val dtlbarb = new Arbiter(3)({new ioDTLB_CPU_req_bundle()})
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }

7
rocket/src/main/scala/util.scala
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@ -163,6 +163,7 @@ class ioPipe[+T <: Data]()(data: => T) extends Bundle
class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
val in = Vec(n) { (new ioDecoupled()) { data } }.flip
val out = (new ioDecoupled()) { data }
val chosen = Bits(log2up(n), OUTPUT)
}
class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
@ -174,8 +175,11 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
}
var dout = io.in(n-1).bits
for (i <- 1 to n-1)
var choose = Bits(n-1)
for (i <- 1 to n-1) {
dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
choose = Mux(io.in(n-1-i).valid, Bits(n-1-i), choose)
}
var vout = io.in(0).valid
for (i <- 1 to n-1)
@ -183,6 +187,7 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
vout <> io.out.valid
dout <> io.out.bits
choose <> io.chosen
}
class RRArbiter[T <: Data](n: Int)(data: => T) extends Component {