riscv/rocket-chip
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change the tlb arbiter to a round robing one

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This commit is contained in:
Yunsup Lee 2012-03-20 15:21:36 -07:00
parent 1cddd5de56
commit 7d7d7f49f9
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/cpu.scala
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@ -37,7 +37,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
{
vu = new vu()
// cpu, vector prefetch, and vector use the DTLB
val dtlbarb = new Arbiter(3)({new ioDTLB_CPU_req_bundle()})
val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()})
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }