hookup vitlb ptw port
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@ -100,6 +100,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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ptw.io.dtlb <> dtlb.io.ptw;
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.vitlb <> vitlb.io.ptw
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.requestor(DMEM_PTW) <> ptw.io.dmem
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arb.io.dmem <> io.dmem
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@ -72,6 +72,7 @@ class ioPTW extends Bundle
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{
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val itlb = new ioTLB_PTW().flip
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val dtlb = new ioTLB_PTW().flip
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val vitlb = new ioTLB_PTW().flip
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val dmem = new ioDmem().flip
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val ptbr = UFix(PADDR_BITS, INPUT);
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}
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@ -84,31 +85,38 @@ class rocketPTW extends Component
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val state = Reg(resetVal = s_ready);
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val r_req_vpn = Reg() { Bits() }
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val r_req_dest = Reg() { Bool() }
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val r_req_dest = Reg() { Bits() }
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val req_addr = Reg() { UFix() };
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val r_resp_ppn = Reg() { Bits() };
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val r_resp_perm = Reg() { Bits() };
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val vpn_idx = Mux(state === s_l2_wait, r_req_vpn(9,0), r_req_vpn(19,10));
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val req_val = io.itlb.req_val || io.dtlb.req_val;
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val req_val = io.itlb.req_val || io.dtlb.req_val || io.vitlb.req_val
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// give ITLB requests priority over DTLB requests
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val req_itlb_val = io.itlb.req_val;
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val req_dtlb_val = io.dtlb.req_val && !io.itlb.req_val;
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when ((state === s_ready) && req_dtlb_val) {
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r_req_vpn := io.dtlb.req_vpn;
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r_req_dest := Bool(true);
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req_addr := Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.dtlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix;
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}
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val req_vitlb_val = io.vitlb.req_val && !io.itlb.req_val && !io.dtlb.req_val
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when ((state === s_ready) && req_itlb_val) {
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r_req_vpn := io.itlb.req_vpn;
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r_req_dest := Bool(false);
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r_req_dest := Bits(0)
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req_addr := Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.itlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix;
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}
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when ((state === s_ready) && req_dtlb_val) {
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r_req_vpn := io.dtlb.req_vpn;
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r_req_dest := Bits(1)
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req_addr := Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.dtlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix;
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}
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when ((state === s_ready) && req_vitlb_val) {
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r_req_vpn := io.vitlb.req_vpn;
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r_req_dest := Bits(2)
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req_addr := Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.vitlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix;
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}
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val dmem_resp_val = Reg(io.dmem.resp_val, resetVal = Bool(false))
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when (dmem_resp_val) {
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req_addr := Cat(io.dmem.resp_data_subword(PADDR_BITS-1, PGIDX_BITS), vpn_idx, Bits(0,3)).toUFix;
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@ -133,22 +141,27 @@ class rocketPTW extends Component
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val resp_ptd = (io.dmem.resp_data_subword(1,0) === Bits(1,2));
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val resp_pte = (io.dmem.resp_data_subword(1,0) === Bits(2,2));
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io.dtlb.req_rdy := (state === s_ready) && !io.itlb.req_val;
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io.itlb.req_rdy := (state === s_ready);
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io.dtlb.resp_val := r_req_dest && resp_val;
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io.itlb.resp_val := !r_req_dest && resp_val;
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io.dtlb.resp_err := r_req_dest && resp_err;
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io.itlb.resp_err := !r_req_dest && resp_err;
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io.dtlb.resp_perm := r_resp_perm;
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io.itlb.resp_perm := r_resp_perm;
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io.itlb.req_rdy := (state === s_ready)
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io.dtlb.req_rdy := (state === s_ready) && !io.itlb.req_val
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io.vitlb.req_rdy := (state === s_ready) && !io.itlb.req_val && !io.dtlb.req_val
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io.itlb.resp_val := r_req_dest === Bits(0) && resp_val
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io.dtlb.resp_val := r_req_dest === Bits(1) && resp_val
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io.vitlb.resp_val := r_req_dest === Bits(2) && resp_val
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io.itlb.resp_err := r_req_dest === Bits(0) && resp_err
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io.dtlb.resp_err := r_req_dest === Bits(1) && resp_err
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io.vitlb.resp_err := r_req_dest === Bits(2) && resp_err
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io.itlb.resp_perm := r_resp_perm
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io.dtlb.resp_perm := r_resp_perm
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io.vitlb.resp_perm:= r_resp_perm
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val resp_ppn =
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Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-11, 0)),
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Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
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r_resp_ppn));
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io.dtlb.resp_ppn := resp_ppn;
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io.itlb.resp_ppn := resp_ppn;
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io.dtlb.resp_ppn := resp_ppn;
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io.vitlb.resp_ppn := resp_ppn;
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// control state machine
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switch (state) {
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