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Commit Graph

2958 Commits

Author SHA1 Message Date
Andrew Waterman
fb827abbfa Use dynamic fesvr library 2014-01-28 03:50:19 -08:00
Andrew Waterman
0266c1f76a Support retirement width > 1 in CSR file 2014-01-24 16:37:40 -08:00
Andrew Waterman
267394d3cc Fix CSR interlocks 2014-01-24 16:37:40 -08:00
Andrew Waterman
1f986d1c96 Branches don't care about the ALU input/function 2014-01-24 16:37:40 -08:00
Andrew Waterman
a1b7774f5d Simplify handling of CAUSE register 2014-01-24 16:37:39 -08:00
Yunsup Lee
ce36d67f05 push tools/tests 2014-01-22 20:18:44 -08:00
Andrew Waterman
3e634aef1d Fix HTIF for cache line sizes other than 64 B 2014-01-22 18:20:36 -08:00
Christopher Celio
a2be21361e Allow ICacheConfig to toggle fetch-width. 2014-01-22 16:19:57 -08:00
Andrew Waterman
7c11cf49b8 Update riscv-tools 2014-01-21 16:23:32 -08:00
Andrew Waterman
b6c6bddb62 Add full CSRRx support and an asm test 2014-01-21 16:20:24 -08:00
Andrew Waterman
a7489920ce Support CSR atomics on all CSRs, not just STATUS 2014-01-21 16:17:39 -08:00
Stephen Twigg
e7ee94bcc8 Merge branch 'master' into hwacha-port 2014-01-21 15:23:05 -08:00
Andrew Waterman
6ba2c1abe5 Use auto-generated CAUSE constants 2014-01-21 15:01:54 -08:00
Stephen Twigg
ee0c4ca291 Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) 2014-01-21 14:48:04 -08:00
Andrew Waterman
6f7ae01b1a More FPU fixes 2014-01-17 14:10:10 -08:00
Andrew Waterman
95de358a96 More of the same FPU fix
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
2014-01-17 14:09:30 -08:00
Andrew Waterman
6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman
cf38001e98 Fix fmv.s.x -> fsd 2014-01-17 03:52:35 -08:00
Yunsup Lee
30b894c2c4 Merge remote-tracking branch 'origin/master' into hwacha-port 2014-01-16 16:04:48 -08:00
Yunsup Lee
6bbbf36979 push accel/rocket dmem port back to rocket 2014-01-16 16:01:41 -08:00
Andrew Waterman
dfc13236d1 Linux works again! 2014-01-16 12:44:29 -08:00
Andrew Waterman
57f4d89c90 Generate D$ replay_next signals correctly 2014-01-16 00:16:09 -08:00
Andrew Waterman
6ebdc4d94e Simplify store conditional failure code generation 2014-01-16 00:15:48 -08:00
Andrew Waterman
31060ea8ae Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
2014-01-14 04:02:43 -08:00
Andrew Waterman
4f1213cb8b Fix Scala integer overflow 2014-01-13 21:45:14 -08:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
a50a1f7d50 Clean up multiplier/divider stuff 2014-01-13 21:37:16 -08:00
Andrew Waterman
4d236979bd Fix very far forward JALs
We were sign-extending from the wrong bit, causing a backwards jump.
2014-01-13 00:55:48 -08:00
Andrew Waterman
c546f66404 Swap JAL/JALR encodings (again) 2014-01-13 00:54:49 -08:00
Quan Nguyen
37b86c89fa Introduce confprec 2013-12-13 03:38:16 -08:00
Quan Nguyen
ebec444ad2 Increase tag width for configurable precision in Hwacha 2013-12-13 03:33:02 -08:00
Andrew Waterman
d99ee1f9c2 Update hardfloat, fixing SFMA unit 2013-12-09 20:31:58 -08:00
Andrew Waterman
07a91bb99a Miscellaneous cleanup 2013-12-09 19:53:14 -08:00
Andrew Waterman
ab6cd9c9e8 Update chisel, rocket 2013-12-09 15:09:48 -08:00
Andrew Waterman
da3135ac9b Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
2013-12-09 15:06:13 -08:00
Andrew Waterman
16d5250924 Correct FP trap behavior on FCSR 2013-12-05 04:18:04 -08:00
Andrew Waterman
5814a90472 Make DecodeLogic interface more flexible 2013-12-05 04:16:48 -08:00
Andrew Waterman
a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
acc0d2b06c Only use LSBs for HTIF control regs
For now, at least...
2013-11-25 04:34:16 -08:00
Andrew Waterman
65b8340cea Mitigate D$ hit -> branch -> NPC critical path 2013-11-24 14:21:03 -08:00
Andrew Waterman
53f726008b Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
2013-11-24 14:21:02 -08:00
Yunsup Lee
1c6f4e91f9 merge origin/master, and push hwacha 2013-11-21 15:02:40 -08:00
Yunsup Lee
d450b85483 Merge branch 'master', remote-tracking branch 'origin' into hwacha 2013-11-21 14:57:38 -08:00
Yunsup Lee
9e6e5adeba push uncore 2013-11-21 14:55:57 -08:00
Yunsup Lee
951226f413 fix slli/slliw encoding bug 2013-11-21 14:46:31 -08:00
Yunsup Lee
25fdf9827f push tests 2013-11-21 14:45:59 -08:00
Yunsup Lee
68e270eeb2 fix slli/slliw encoding bug 2013-11-21 14:44:58 -08:00
Yunsup Lee
5642194834 push hwacha to consistent state 2013-11-20 16:44:33 -08:00
Yunsup Lee
056bb156ca make CacheConstants an object 2013-11-20 16:43:55 -08:00