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Commit Graph

3686 Commits

Author SHA1 Message Date
Howard Mao
9b3faff5a5 add id field to write data channel in TL -> AXI converter 2016-04-19 09:46:31 -07:00
Howard Mao
1967186a96 add id field to NastiWriteDataChannel 2016-04-19 09:39:45 -07:00
Howard Mao
42c4d1e51f add NastiMemoryDemux 2016-04-19 09:39:15 -07:00
Howard Mao
0bf8d07aba make AtosSerializedIO clock divisible 2016-04-19 09:39:15 -07:00
Howard Mao
1dc8af894e fix serializer/deserializer and add Atos serdes/desser 2016-04-19 09:39:15 -07:00
Howard Mao
82cacfbc5e add NastiMemoryDemux to unit tests 2016-04-19 09:34:42 -07:00
Howard Mao
075fdfb847 use Atos serdes/desser in Atos unit test 2016-04-19 09:34:12 -07:00
Howard Mao
ee66da603a move AtosConverterTest into UnitTestSuite 2016-04-19 09:34:12 -07:00
Howard Mao
d19aaf8d89 test AtoS conversions and SERDES 2016-04-19 09:33:05 -07:00
Palmer Dabbelt
7c33d88861 Merge pull request #90 from ucb-bar/elaborate-once
Bump Chisel3, to elaborate circuits once
2016-04-18 21:04:55 -07:00
Palmer Dabbelt
85c86994a0 Bump Chisel3, to elaborate circuits once 2016-04-18 14:54:17 -07:00
Matthew Naylor
cbfd7fd13a Remove tracegen scripts, now in groundtest
And bump groundtest.
2016-04-14 14:01:48 -07:00
Howard Mao
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Howard Mao
d5153bf42e don't connect unnecessary wires in regression test 2016-04-12 15:38:55 -07:00
Howard Mao
55df7d97cc add regression test for put immediately before put block 2016-04-12 15:38:55 -07:00
Howard Mao
485d8d7f9c fix nasti converter tests 2016-04-12 15:38:55 -07:00
Howard Mao
b2e15cd9bc NASTI to SMI converter test should also test TL to NASTI conversion 2016-04-12 15:38:55 -07:00
Howard Mao
0c562277db test Nasti to SMI converter with SMI datawidth being different 2016-04-12 15:38:55 -07:00
Howard Mao
152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst 2016-04-07 11:20:16 -07:00
Howard Mao
f88b6932ce don't add pending reads if data is already available 2016-04-06 15:43:21 -07:00
Christopher Celio
2d6f35525e Added Field[Int] to SFMALatency/DFMALatency params 2016-04-06 14:50:57 -07:00
mwachs5
a81334f505 Update README links to point to this repo 2016-04-06 14:10:04 -07:00
Matthew Naylor
b2eabf4a9f Add tracegen scripts inc. bugfix from @mwachs5
A step towards moving the tracegen scripts from rocket-chip to
groundtest.  I will raise an issue requesting that the scripts are now
removed from rocket-chip by someone with write access.

I have updated the README to account for the move.

This commit includes a bugfix from @mwachs5 (with slight mods by me)
relating to potential division by zero in toaxe.py.
2016-04-06 15:15:48 +01:00
Howard Mao
31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00
Howard Mao
f68a7dabdf fix AXI -> TL converter 2016-04-04 19:42:25 -07:00
Howard Mao
f956d4edfb NASTI does not right-justify data; fix in converter 2016-04-01 20:55:00 -07:00
Henry Cook
c292a07ace Bugfix for merged voluntary releases in L2Cache.
Track pending release beats for voluntary releases that are merged by Acquire Trackers.
Closes #23 and #24.
2016-04-01 19:57:47 -07:00
Andrew Waterman
7285f5e6bf Don't drive D$ kill/phys signals for SimpleHellaCacheIF
They don't do anything.
2016-04-01 19:31:54 -07:00
Andrew Waterman
51e0870e23 Separate I$ and D$ interface signals that span clock cycles
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
Howard Mao
d66d8f0cd4 fix SMI converter 2016-04-01 18:32:15 -07:00
Andrew Waterman
c4c6bd1040 Bump rocket.
Closes #84.
2016-04-01 18:20:32 -07:00
Andrew Waterman
b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Andrew Waterman
46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
Andrew Waterman
cd9e07d8e7 Update sbt to 0.13.11 2016-04-01 18:18:08 -07:00
Andrew Waterman
bd3dba7f66 Fix LR/SC livelock bug
Closes #74.
2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096 LRSC fix. RocketChipNetwork moved to uncore. 2016-04-01 18:09:00 -07:00
Andrew Waterman
dc662f28a0 Specify width on s1_pc to avoid width inference problem 2016-04-01 17:28:42 -07:00
Andrew Waterman
72f7f71eb5 No need to allow finishes to be sent in s_refill_resp state
This is a hold-over from when writebacks needed finish messages.
2016-04-01 16:19:57 -07:00
Henry Cook
82bdf3afcb Fix LRSC starvation bug by punching Finish messages out to caching clients via a new TileLinkNetworkPort. 2016-04-01 16:17:27 -07:00
Henry Cook
78bc18736e LRSC startvation fix: HellaCache generates its own Finish messages again. 2016-04-01 16:04:25 -07:00
Andrew Waterman
37b9051762 No need to validate npc if BTB is disabled 2016-04-01 15:54:57 -07:00
Andrew Waterman
4480d1e817 Don't compile BTB when nEntries=0 2016-04-01 15:14:45 -07:00
Andrew Waterman
d406dc1231 Remove vestigial BTB enable option 2016-04-01 15:14:34 -07:00
Andrew Waterman
8957b5e973 Improve simulation speed of BasicCrossbar 2016-04-01 13:28:11 -07:00
Howard Mao
5337c7d22d add more complicated memtests to travis 2016-03-31 18:42:14 -07:00
Howard Mao
4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao
3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector 2016-03-31 18:15:51 -07:00
Henry Cook
54dd82ff76 bugfix for WB data buffer 2016-03-31 17:53:49 -07:00