Yunsup Lee
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81d711e892
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fix D$ bug; now D$ doesn't respond to prefetches
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2012-11-17 20:06:13 -08:00 |
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Andrew Waterman
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7bcf59a18f
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support continous compilation via "make test"
for c++ emulator only, for now
|
2012-11-17 19:58:18 -08:00 |
|
Andrew Waterman
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b58214d7e3
|
remove more global constants
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2012-11-17 17:25:43 -08:00 |
|
Andrew Waterman
|
29bc361d6c
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remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
cf05b604b3
|
upgrade to new rocket; improve vlsi makefiles
|
2012-11-17 07:21:29 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
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cc067026a2
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pipeline D$ response -> FPU regfile
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2012-11-17 06:48:11 -08:00 |
|
Andrew Waterman
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e68b039133
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fix misc. D$ control bugs
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2012-11-17 06:47:27 -08:00 |
|
Andrew Waterman
|
dad7b71062
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provide cmd/addr with cache response
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2012-11-16 21:26:12 -08:00 |
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Andrew Waterman
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cb8ac73045
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provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
Andrew Waterman
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672e904c86
|
update to new rocket/uncore
|
2012-11-16 02:41:50 -08:00 |
|
Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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3e6dc35809
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issue self-probes for uncached read transactions
this facilitates I$ coherence. but it seems like a hack and perhaps
the mechanism should be rethought.
|
2012-11-16 02:37:56 -08:00 |
|
Andrew Waterman
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a90a1790a5
|
improve tlb qor
|
2012-11-16 01:59:38 -08:00 |
|
Andrew Waterman
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ff8c736d94
|
move icache invalidate out of request bundle
|
2012-11-16 01:55:45 -08:00 |
|
Andrew Waterman
|
6d10115b19
|
fix D$ tag width
|
2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
|
1a91637673
|
refactored vector queue interface
|
2012-11-07 01:16:02 -08:00 |
|
Yunsup Lee
|
be1980dd2d
|
refactored vector queue interface
|
2012-11-07 01:15:33 -08:00 |
|
Yunsup Lee
|
29d4c0b857
|
refactored tlb
|
2012-11-06 23:54:14 -08:00 |
|
Yunsup Lee
|
8764fe786a
|
refactored vector tlb
|
2012-11-06 23:53:52 -08:00 |
|
Yunsup Lee
|
9a02298f6f
|
andrew's fix for tlb lockup
|
2012-11-06 23:52:58 -08:00 |
|
Andrew Waterman
|
e2afae011a
|
factor out global constants
|
2012-11-06 08:18:40 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
|
1305372ce7
|
refactor flush logic
|
2012-11-05 23:01:08 -08:00 |
|
Yunsup Lee
|
9844ba1c1d
|
revamp the vector unit with the new frontend
HAVE_PVFB is still broken, we need to multi-thread the frontend
|
2012-11-05 01:44:02 -08:00 |
|
Yunsup Lee
|
ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|
Yunsup Lee
|
2a25307a8f
|
revamp the vector unit with the new frontend
|
2012-11-05 01:35:55 -08:00 |
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
|
5e103054fd
|
fix bug in quine mccluskey
|
2012-11-05 00:28:25 -08:00 |
|
Yunsup Lee
|
dd6ee2571d
|
add vector vm tests
|
2012-11-04 19:29:56 -08:00 |
|
Andrew Waterman
|
0c372fc9ec
|
refactor I$ config into RocketConfiguration
|
2012-11-04 17:00:19 -08:00 |
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
Andrew Waterman
|
4ed2d614a2
|
update to new rocket; retime fpu in dc-syn
|
2012-11-04 16:43:02 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
bd2d61de03
|
use 8T SRAM for I$; gate clock more aggressively
|
2012-11-04 16:39:25 -08:00 |
|
Andrew Waterman
|
fedee6c67d
|
add generic error correcting codes
|
2012-10-30 01:03:47 -07:00 |
|
Henry Cook
|
0cd0f8a9db
|
Initial version of migratory protocol
|
2012-10-23 18:01:53 -07:00 |
|
Henry Cook
|
538b23c223
|
Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
|
2012-10-23 12:52:59 -07:00 |
|
Henry Cook
|
17d2bd8926
|
Initial version of sbt tasks (elaborate task with no parameters)
|
2012-10-23 12:52:00 -07:00 |
|
Yunsup Lee
|
3edc1f42aa
|
revamp the backup memory link in the vlsi backend
|
2012-10-23 03:31:34 -07:00 |
|
Andrew Waterman
|
367b5489d1
|
first crack at continuous compilation/testing flow
try it out: cd emulator; make test
|
2012-10-19 04:09:07 -07:00 |
|
Andrew Waterman
|
1ad928cfe2
|
directly integrate dramsim build
also, build it as a static library to simplify dependencies
|
2012-10-18 18:59:37 -07:00 |
|
Andrew Waterman
|
edf0eeed01
|
integrate updated rocket/uncore
|
2012-10-18 17:51:41 -07:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Andrew Waterman
|
2aecb0024f
|
UncoreConfiguration now contains coherence policy
|
2012-10-18 16:57:28 -07:00 |
|
Andrew Waterman
|
ffda0e41a9
|
parameterize width of MemSerdes/MemDesser
|
2012-10-18 16:56:36 -07:00 |
|
Henry Cook
|
e2eb7ce8e9
|
Cleanup git incompetence
|
2012-10-16 16:54:58 -07:00 |
|